PPCTargetMachine.cpp revision 09fdc7baae1b6905fe18df48e2278e74d4e39ccd 
1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCTargetMachine.h"
15#include "PPC.h"
16#include "llvm/PassManager.h"
17#include "llvm/MC/MCStreamer.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/Target/TargetOptions.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Support/FormattedStream.h"
22#include "llvm/Support/TargetRegistry.h"
23using namespace llvm;
24
25static cl::
26opt<bool> EnableCTRLoops("enable-ppc-ctrloops", cl::Hidden,
27                        cl::desc("Enable CTR loops for PPC"));
28
29extern "C" void LLVMInitializePowerPCTarget() {
30  // Register the targets
31  RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32  RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33}
34
35PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
36                                   StringRef CPU, StringRef FS,
37                                   const TargetOptions &Options,
38                                   Reloc::Model RM, CodeModel::Model CM,
39                                   CodeGenOpt::Level OL,
40                                   bool is64Bit)
41  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42    Subtarget(TT, CPU, FS, is64Bit),
43    DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
44    FrameLowering(Subtarget), JITInfo(*this, is64Bit),
45    TLInfo(*this), TSInfo(*this),
46    InstrItins(Subtarget.getInstrItineraryData()) {
47
48  // The binutils for the BG/P are too old for CFI.
49  if (Subtarget.isBGP())
50    setMCUseCFI(false);
51}
52
53void PPC32TargetMachine::anchor() { }
54
55PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
56                                       StringRef CPU, StringRef FS,
57                                       const TargetOptions &Options,
58                                       Reloc::Model RM, CodeModel::Model CM,
59                                       CodeGenOpt::Level OL)
60  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
61}
62
63void PPC64TargetMachine::anchor() { }
64
65PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
66                                       StringRef CPU,  StringRef FS,
67                                       const TargetOptions &Options,
68                                       Reloc::Model RM, CodeModel::Model CM,
69                                       CodeGenOpt::Level OL)
70  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
71}
72
73
74//===----------------------------------------------------------------------===//
75// Pass Pipeline Configuration
76//===----------------------------------------------------------------------===//
77
78namespace {
79/// PPC Code Generator Pass Configuration Options.
80class PPCPassConfig : public TargetPassConfig {
81public:
82  PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
83    : TargetPassConfig(TM, PM) {}
84
85  PPCTargetMachine &getPPCTargetMachine() const {
86    return getTM<PPCTargetMachine>();
87  }
88
89  virtual bool addPreRegAlloc();
90  virtual bool addInstSelector();
91  virtual bool addPreEmitPass();
92};
93} // namespace
94
95TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
96  TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
97
98  // Override this for PowerPC.  Tail merging happily breaks up instruction issue
99  // groups, which typically degrades performance.
100  PassConfig->setEnableTailMerge(false);
101
102  return PassConfig;
103}
104
105bool PPCPassConfig::addPreRegAlloc() {
106  // FIXME: Once this can be enabled by default, this condition should read:
107  // if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
108  if (EnableCTRLoops)
109    PM->add(createPPCCTRLoops());
110
111  return false;
112}
113
114bool PPCPassConfig::addInstSelector() {
115  // Install an instruction selector.
116  PM->add(createPPCISelDag(getPPCTargetMachine()));
117  return false;
118}
119
120bool PPCPassConfig::addPreEmitPass() {
121  // Must run branch selection immediately preceding the asm printer.
122  PM->add(createPPCBranchSelectionPass());
123  return false;
124}
125
126bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
127                                      JITCodeEmitter &JCE) {
128  // FIXME: This should be moved to TargetJITInfo!!
129  if (Subtarget.isPPC64())
130    // Temporary workaround for the inability of PPC64 JIT to handle jump
131    // tables.
132    Options.DisableJumpTables = true;
133
134  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
135  // writing?
136  Subtarget.SetJITMode();
137
138  // Machine code emitter pass for PowerPC.
139  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
140
141  return false;
142}
143