PPCTargetMachine.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCTargetMachine.h"
15#include "PPC.h"
16#include "llvm/CodeGen/Passes.h"
17#include "llvm/MC/MCStreamer.h"
18#include "llvm/PassManager.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Support/FormattedStream.h"
21#include "llvm/Support/TargetRegistry.h"
22#include "llvm/Target/TargetOptions.h"
23using namespace llvm;
24
25static cl::
26opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27                        cl::desc("Disable CTR loops for PPC"));
28
29static cl::opt<bool>
30VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
31  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
32
33extern "C" void LLVMInitializePowerPCTarget() {
34  // Register the targets
35  RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
36  RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
37  RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
38}
39
40/// Return the datalayout string of a subtarget.
41static std::string getDataLayoutString(const PPCSubtarget &ST) {
42  const Triple &T = ST.getTargetTriple();
43
44  std::string Ret;
45
46  // Most PPC* platforms are big endian, PPC64LE is little endian.
47  if (ST.isLittleEndian())
48    Ret = "e";
49  else
50    Ret = "E";
51
52  Ret += DataLayout::getManglingComponent(T);
53
54  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
55  // pointers.
56  if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
57    Ret += "-p:32:32";
58
59  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
60  // documentation are wrong; these are correct (i.e. "what gcc does").
61  if (ST.isPPC64() || ST.isSVR4ABI())
62    Ret += "-i64:64";
63  else
64    Ret += "-f64:32:64";
65
66  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
67  if (ST.isPPC64())
68    Ret += "-n32:64";
69  else
70    Ret += "-n32";
71
72  return Ret;
73}
74
75PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
76                                   StringRef CPU, StringRef FS,
77                                   const TargetOptions &Options,
78                                   Reloc::Model RM, CodeModel::Model CM,
79                                   CodeGenOpt::Level OL,
80                                   bool is64Bit)
81  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
82    Subtarget(TT, CPU, FS, is64Bit, OL),
83    DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
84    FrameLowering(Subtarget), JITInfo(*this, is64Bit),
85    TLInfo(*this), TSInfo(*this),
86    InstrItins(Subtarget.getInstrItineraryData()) {
87  initAsmInfo();
88}
89
90void PPC32TargetMachine::anchor() { }
91
92PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
93                                       StringRef CPU, StringRef FS,
94                                       const TargetOptions &Options,
95                                       Reloc::Model RM, CodeModel::Model CM,
96                                       CodeGenOpt::Level OL)
97  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
98}
99
100void PPC64TargetMachine::anchor() { }
101
102PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
103                                       StringRef CPU,  StringRef FS,
104                                       const TargetOptions &Options,
105                                       Reloc::Model RM, CodeModel::Model CM,
106                                       CodeGenOpt::Level OL)
107  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
108}
109
110
111//===----------------------------------------------------------------------===//
112// Pass Pipeline Configuration
113//===----------------------------------------------------------------------===//
114
115namespace {
116/// PPC Code Generator Pass Configuration Options.
117class PPCPassConfig : public TargetPassConfig {
118public:
119  PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
120    : TargetPassConfig(TM, PM) {}
121
122  PPCTargetMachine &getPPCTargetMachine() const {
123    return getTM<PPCTargetMachine>();
124  }
125
126  const PPCSubtarget &getPPCSubtarget() const {
127    return *getPPCTargetMachine().getSubtargetImpl();
128  }
129
130  virtual bool addPreISel();
131  virtual bool addILPOpts();
132  virtual bool addInstSelector();
133  virtual bool addPreRegAlloc();
134  virtual bool addPreSched2();
135  virtual bool addPreEmitPass();
136};
137} // namespace
138
139TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
140  return new PPCPassConfig(this, PM);
141}
142
143bool PPCPassConfig::addPreISel() {
144  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
145    addPass(createPPCCTRLoops(getPPCTargetMachine()));
146
147  return false;
148}
149
150bool PPCPassConfig::addILPOpts() {
151  if (getPPCSubtarget().hasISEL()) {
152    addPass(&EarlyIfConverterID);
153    return true;
154  }
155
156  return false;
157}
158
159bool PPCPassConfig::addInstSelector() {
160  // Install an instruction selector.
161  addPass(createPPCISelDag(getPPCTargetMachine()));
162
163#ifndef NDEBUG
164  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
165    addPass(createPPCCTRLoopsVerify());
166#endif
167
168  if (getPPCSubtarget().hasVSX())
169    addPass(createPPCVSXCopyPass());
170
171  return false;
172}
173
174bool PPCPassConfig::addPreRegAlloc() {
175  if (getPPCSubtarget().hasVSX()) {
176    initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
177    insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
178               &PPCVSXFMAMutateID);
179  }
180
181  return false;
182}
183
184bool PPCPassConfig::addPreSched2() {
185  if (getPPCSubtarget().hasVSX())
186    addPass(createPPCVSXCopyCleanupPass());
187
188  if (getOptLevel() != CodeGenOpt::None)
189    addPass(&IfConverterID);
190
191  return true;
192}
193
194bool PPCPassConfig::addPreEmitPass() {
195  if (getOptLevel() != CodeGenOpt::None)
196    addPass(createPPCEarlyReturnPass());
197  // Must run branch selection immediately preceding the asm printer.
198  addPass(createPPCBranchSelectionPass());
199  return false;
200}
201
202bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
203                                      JITCodeEmitter &JCE) {
204  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
205  // writing?
206  Subtarget.SetJITMode();
207
208  // Machine code emitter pass for PowerPC.
209  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
210
211  return false;
212}
213
214void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
215  // Add first the target-independent BasicTTI pass, then our PPC pass. This
216  // allows the PPC pass to delegate to the target independent layer when
217  // appropriate.
218  PM.add(createBasicTargetTransformInfoPass(this));
219  PM.add(createPPCTargetTransformInfoPass(this));
220}
221
222