PPCTargetMachine.cpp revision 61f1e3db43e556f495b6b9360d2f550291f78471 
1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPC.h"
15#include "PPCTargetMachine.h"
16#include "llvm/PassManager.h"
17#include "llvm/MC/MCStreamer.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/Target/TargetOptions.h"
20#include "llvm/Support/FormattedStream.h"
21#include "llvm/Support/TargetRegistry.h"
22using namespace llvm;
23
24extern "C" void LLVMInitializePowerPCTarget() {
25  // Register the targets
26  RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
27  RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
28}
29
30PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
31                                   StringRef CPU, StringRef FS,
32                                   const TargetOptions &Options,
33                                   Reloc::Model RM, CodeModel::Model CM,
34                                   CodeGenOpt::Level OL,
35                                   bool is64Bit)
36  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
37    Subtarget(TT, CPU, FS, is64Bit),
38    DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
39    FrameLowering(Subtarget), JITInfo(*this, is64Bit),
40    TLInfo(*this), TSInfo(*this),
41    InstrItins(Subtarget.getInstrItineraryData()) {
42}
43
44void PPC32TargetMachine::anchor() { }
45
46PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
47                                       StringRef CPU, StringRef FS,
48                                       const TargetOptions &Options,
49                                       Reloc::Model RM, CodeModel::Model CM,
50                                       CodeGenOpt::Level OL)
51  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
52}
53
54void PPC64TargetMachine::anchor() { }
55
56PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
57                                       StringRef CPU,  StringRef FS,
58                                       const TargetOptions &Options,
59                                       Reloc::Model RM, CodeModel::Model CM,
60                                       CodeGenOpt::Level OL)
61  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
62}
63
64
65//===----------------------------------------------------------------------===//
66// Pass Pipeline Configuration
67//===----------------------------------------------------------------------===//
68
69namespace {
70/// PPC Code Generator Pass Configuration Options.
71class PPCPassConfig : public TargetPassConfig {
72public:
73  PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
74    : TargetPassConfig(TM, PM) {}
75
76  PPCTargetMachine &getPPCTargetMachine() const {
77    return getTM<PPCTargetMachine>();
78  }
79
80  virtual bool addInstSelector();
81  virtual bool addPreEmitPass();
82};
83} // namespace
84
85TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
86  TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
87
88  // Override this for PowerPC.  Tail merging happily breaks up instruction issue
89  // groups, which typically degrades performance.
90  PassConfig->setEnableTailMerge(false);
91
92  return PassConfig;
93}
94
95bool PPCPassConfig::addInstSelector() {
96  // Install an instruction selector.
97  PM.add(createPPCISelDag(getPPCTargetMachine()));
98  return false;
99}
100
101bool PPCPassConfig::addPreEmitPass() {
102  // Must run branch selection immediately preceding the asm printer.
103  PM.add(createPPCBranchSelectionPass());
104  return false;
105}
106
107bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
108                                      JITCodeEmitter &JCE) {
109  // FIXME: This should be moved to TargetJITInfo!!
110  if (Subtarget.isPPC64())
111    // Temporary workaround for the inability of PPC64 JIT to handle jump
112    // tables.
113    Options.DisableJumpTables = true;
114
115  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
116  // writing?
117  Subtarget.SetJITMode();
118
119  // Machine code emitter pass for PowerPC.
120  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
121
122  return false;
123}
124