PPCTargetMachine.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Top-level implementation for the PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCTargetMachine.h" 15#include "PPC.h" 16#include "llvm/CodeGen/Passes.h" 17#include "llvm/MC/MCStreamer.h" 18#include "llvm/PassManager.h" 19#include "llvm/Support/CommandLine.h" 20#include "llvm/Support/FormattedStream.h" 21#include "llvm/Support/TargetRegistry.h" 22#include "llvm/Target/TargetOptions.h" 23using namespace llvm; 24 25static cl:: 26opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, 27 cl::desc("Disable CTR loops for PPC")); 28 29static cl::opt<bool> 30VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", 31 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early")); 32 33extern "C" void LLVMInitializePowerPCTarget() { 34 // Register the targets 35 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target); 36 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target); 37 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget); 38} 39 40/// Return the datalayout string of a subtarget. 41static std::string getDataLayoutString(const PPCSubtarget &ST) { 42 const Triple &T = ST.getTargetTriple(); 43 44 std::string Ret; 45 46 // Most PPC* platforms are big endian, PPC64LE is little endian. 47 if (ST.isLittleEndian()) 48 Ret = "e"; 49 else 50 Ret = "E"; 51 52 Ret += DataLayout::getManglingComponent(T); 53 54 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit 55 // pointers. 56 if (!ST.isPPC64() || T.getOS() == Triple::Lv2) 57 Ret += "-p:32:32"; 58 59 // Note, the alignment values for f64 and i64 on ppc64 in Darwin 60 // documentation are wrong; these are correct (i.e. "what gcc does"). 61 if (ST.isPPC64() || ST.isSVR4ABI()) 62 Ret += "-i64:64"; 63 else 64 Ret += "-f64:32:64"; 65 66 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones. 67 if (ST.isPPC64()) 68 Ret += "-n32:64"; 69 else 70 Ret += "-n32"; 71 72 return Ret; 73} 74 75PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, 76 StringRef CPU, StringRef FS, 77 const TargetOptions &Options, 78 Reloc::Model RM, CodeModel::Model CM, 79 CodeGenOpt::Level OL, 80 bool is64Bit) 81 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 82 Subtarget(TT, CPU, FS, is64Bit, OL), 83 DL(getDataLayoutString(Subtarget)), InstrInfo(*this), 84 FrameLowering(Subtarget), JITInfo(*this, is64Bit), 85 TLInfo(*this), TSInfo(*this), 86 InstrItins(Subtarget.getInstrItineraryData()) { 87 initAsmInfo(); 88} 89 90void PPC32TargetMachine::anchor() { } 91 92PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, 93 StringRef CPU, StringRef FS, 94 const TargetOptions &Options, 95 Reloc::Model RM, CodeModel::Model CM, 96 CodeGenOpt::Level OL) 97 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 98} 99 100void PPC64TargetMachine::anchor() { } 101 102PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, 103 StringRef CPU, StringRef FS, 104 const TargetOptions &Options, 105 Reloc::Model RM, CodeModel::Model CM, 106 CodeGenOpt::Level OL) 107 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 108} 109 110 111//===----------------------------------------------------------------------===// 112// Pass Pipeline Configuration 113//===----------------------------------------------------------------------===// 114 115namespace { 116/// PPC Code Generator Pass Configuration Options. 117class PPCPassConfig : public TargetPassConfig { 118public: 119 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM) 120 : TargetPassConfig(TM, PM) {} 121 122 PPCTargetMachine &getPPCTargetMachine() const { 123 return getTM<PPCTargetMachine>(); 124 } 125 126 const PPCSubtarget &getPPCSubtarget() const { 127 return *getPPCTargetMachine().getSubtargetImpl(); 128 } 129 130 bool addPreISel() override; 131 bool addILPOpts() override; 132 bool addInstSelector() override; 133 bool addPreRegAlloc() override; 134 bool addPreSched2() override; 135 bool addPreEmitPass() override; 136}; 137} // namespace 138 139TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { 140 return new PPCPassConfig(this, PM); 141} 142 143bool PPCPassConfig::addPreISel() { 144 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) 145 addPass(createPPCCTRLoops(getPPCTargetMachine())); 146 147 return false; 148} 149 150bool PPCPassConfig::addILPOpts() { 151 addPass(&EarlyIfConverterID); 152 return true; 153} 154 155bool PPCPassConfig::addInstSelector() { 156 // Install an instruction selector. 157 addPass(createPPCISelDag(getPPCTargetMachine())); 158 159#ifndef NDEBUG 160 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) 161 addPass(createPPCCTRLoopsVerify()); 162#endif 163 164 addPass(createPPCVSXCopyPass()); 165 return false; 166} 167 168bool PPCPassConfig::addPreRegAlloc() { 169 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry()); 170 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID, 171 &PPCVSXFMAMutateID); 172 return false; 173} 174 175bool PPCPassConfig::addPreSched2() { 176 addPass(createPPCVSXCopyCleanupPass()); 177 178 if (getOptLevel() != CodeGenOpt::None) 179 addPass(&IfConverterID); 180 181 return true; 182} 183 184bool PPCPassConfig::addPreEmitPass() { 185 if (getOptLevel() != CodeGenOpt::None) 186 addPass(createPPCEarlyReturnPass()); 187 // Must run branch selection immediately preceding the asm printer. 188 addPass(createPPCBranchSelectionPass()); 189 return false; 190} 191 192bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, 193 JITCodeEmitter &JCE) { 194 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho 195 // writing? 196 Subtarget.SetJITMode(); 197 198 // Machine code emitter pass for PowerPC. 199 PM.add(createPPCJITCodeEmitterPass(*this, JCE)); 200 201 return false; 202} 203 204void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) { 205 // Add first the target-independent BasicTTI pass, then our PPC pass. This 206 // allows the PPC pass to delegate to the target independent layer when 207 // appropriate. 208 PM.add(createBasicTargetTransformInfoPass(this)); 209 PM.add(createPPCTargetTransformInfoPass(this)); 210} 211 212