PPCTargetMachine.cpp revision e1e0f485f9721a0c4236326f32d0a48561a1af7a 
1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPC.h"
15#include "PPCMCAsmInfo.h"
16#include "PPCTargetMachine.h"
17#include "llvm/PassManager.h"
18#include "llvm/Target/TargetOptions.h"
19#include "llvm/Target/TargetRegistry.h"
20#include "llvm/Support/FormattedStream.h"
21using namespace llvm;
22
23static const MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
24  Triple TheTriple(TT);
25  bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
26  if (TheTriple.getOS() == Triple::Darwin)
27    return new PPCMCAsmInfoDarwin(isPPC64);
28  return new PPCLinuxMCAsmInfo(isPPC64);
29
30}
31
32extern "C" void LLVMInitializePowerPCTarget() {
33  // Register the targets
34  RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
35  RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
36
37  RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo);
38  RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo);
39}
40
41
42PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
43                                   const std::string &FS, bool is64Bit)
44  : LLVMTargetMachine(T, TT),
45    Subtarget(TT, FS, is64Bit),
46    DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
47    FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
48    InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
49
50  if (getRelocationModel() == Reloc::Default) {
51    if (Subtarget.isDarwin())
52      setRelocationModel(Reloc::DynamicNoPIC);
53    else
54      setRelocationModel(Reloc::Static);
55  }
56}
57
58/// Override this for PowerPC.  Tail merging happily breaks up instruction issue
59/// groups, which typically degrades performance.
60bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
61
62PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
63                                       const std::string &FS)
64  : PPCTargetMachine(T, TT, FS, false) {
65}
66
67
68PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
69                                       const std::string &FS)
70  : PPCTargetMachine(T, TT, FS, true) {
71}
72
73
74//===----------------------------------------------------------------------===//
75// Pass Pipeline Configuration
76//===----------------------------------------------------------------------===//
77
78bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
79                                       CodeGenOpt::Level OptLevel) {
80  // Install an instruction selector.
81  PM.add(createPPCISelDag(*this));
82  return false;
83}
84
85bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
86                                      CodeGenOpt::Level OptLevel) {
87  // Must run branch selection immediately preceding the asm printer.
88  PM.add(createPPCBranchSelectionPass());
89  return false;
90}
91
92bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
93                                      CodeGenOpt::Level OptLevel,
94                                      MachineCodeEmitter &MCE) {
95  // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
96  // FIXME: This should be moved to TargetJITInfo!!
97  if (Subtarget.isPPC64()) {
98    // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
99    // instructions to materialize arbitrary global variable + function +
100    // constant pool addresses.
101    setRelocationModel(Reloc::PIC_);
102    // Temporary workaround for the inability of PPC64 JIT to handle jump
103    // tables.
104    DisableJumpTables = true;
105  } else {
106    setRelocationModel(Reloc::Static);
107  }
108
109  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
110  // writing?
111  Subtarget.SetJITMode();
112
113  // Machine code emitter pass for PowerPC.
114  PM.add(createPPCCodeEmitterPass(*this, MCE));
115
116  return false;
117}
118
119bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
120                                      CodeGenOpt::Level OptLevel,
121                                      JITCodeEmitter &JCE) {
122  // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
123  // FIXME: This should be moved to TargetJITInfo!!
124  if (Subtarget.isPPC64()) {
125    // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
126    // instructions to materialize arbitrary global variable + function +
127    // constant pool addresses.
128    setRelocationModel(Reloc::PIC_);
129    // Temporary workaround for the inability of PPC64 JIT to handle jump
130    // tables.
131    DisableJumpTables = true;
132  } else {
133    setRelocationModel(Reloc::Static);
134  }
135
136  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
137  // writing?
138  Subtarget.SetJITMode();
139
140  // Machine code emitter pass for PowerPC.
141  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
142
143  return false;
144}
145
146bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
147                                      CodeGenOpt::Level OptLevel,
148                                      ObjectCodeEmitter &OCE) {
149  // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
150  // FIXME: This should be moved to TargetJITInfo!!
151  if (Subtarget.isPPC64()) {
152    // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
153    // instructions to materialize arbitrary global variable + function +
154    // constant pool addresses.
155    setRelocationModel(Reloc::PIC_);
156    // Temporary workaround for the inability of PPC64 JIT to handle jump
157    // tables.
158    DisableJumpTables = true;
159  } else {
160    setRelocationModel(Reloc::Static);
161  }
162
163  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
164  // writing?
165  Subtarget.SetJITMode();
166
167  // Machine code emitter pass for PowerPC.
168  PM.add(createPPCObjectCodeEmitterPass(*this, OCE));
169
170  return false;
171}
172
173bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
174                                            CodeGenOpt::Level OptLevel,
175                                            MachineCodeEmitter &MCE) {
176  // Machine code emitter pass for PowerPC.
177  PM.add(createPPCCodeEmitterPass(*this, MCE));
178  return false;
179}
180
181bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
182                                            CodeGenOpt::Level OptLevel,
183                                            JITCodeEmitter &JCE) {
184  // Machine code emitter pass for PowerPC.
185  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
186  return false;
187}
188
189bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
190                                            CodeGenOpt::Level OptLevel,
191                                            ObjectCodeEmitter &OCE) {
192  // Machine code emitter pass for PowerPC.
193  PM.add(createPPCObjectCodeEmitterPass(*this, OCE));
194  return false;
195}
196
197/// getLSDAEncoding - Returns the LSDA pointer encoding. The choices are 4-byte,
198/// 8-byte, and target default. The CIE is hard-coded to indicate that the LSDA
199/// pointer in the FDE section is an "sdata4", and should be encoded as a 4-byte
200/// pointer by default. However, some systems may require a different size due
201/// to bugs or other conditions. We will default to a 4-byte encoding unless the
202/// system tells us otherwise.
203///
204/// The issue is when the CIE says their is an LSDA. That mandates that every
205/// FDE have an LSDA slot. But if the function does not need an LSDA. There
206/// needs to be some way to signify there is none. The LSDA is encoded as
207/// pc-rel. But you don't look for some magic value after adding the pc. You
208/// have to look for a zero before adding the pc. The problem is that the size
209/// of the zero to look for depends on the encoding. The unwinder bug in SL is
210/// that it always checks for a pointer-size zero. So on x86_64 it looks for 8
211/// bytes of zero. If you have an LSDA, it works fine since the 8-bytes are
212/// non-zero so it goes ahead and then reads the value based on the encoding.
213/// But if you use sdata4 and there is no LSDA, then the test for zero gives a
214/// false negative and the unwinder thinks there is an LSDA.
215///
216/// FIXME: This call-back isn't good! We should be using the correct encoding
217/// regardless of the system. However, there are some systems which have bugs
218/// that prevent this from occuring.
219DwarfLSDAEncoding::Encoding PPCTargetMachine::getLSDAEncoding() const {
220  if (Subtarget.isDarwin() && Subtarget.getDarwinVers() != 10)
221    return DwarfLSDAEncoding::Default;
222
223  return DwarfLSDAEncoding::EightByte;
224}
225