AMDGPU.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9
10// Include AMDIL TD files
11include "AMDILBase.td"
12
13//===----------------------------------------------------------------------===//
14// Subtarget Features
15//===----------------------------------------------------------------------===//
16
17// Debugging Features
18
19def FeatureDumpCode : SubtargetFeature <"DumpCode",
20        "DumpCode",
21        "true",
22        "Dump MachineInstrs in the CodeEmitter">;
23
24def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
25        "EnableIRStructurizer",
26        "false",
27        "Disable IR Structurizer">;
28
29// Target features
30
31def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
32        "EnableIfCvt",
33        "false",
34        "Disable the if conversion pass">;
35
36def FeatureFP64     : SubtargetFeature<"fp64",
37        "FP64",
38        "true",
39        "Enable 64bit double precision operations">;
40
41def Feature64BitPtr : SubtargetFeature<"64BitPtr",
42        "Is64bit",
43        "true",
44        "Specify if 64bit addressing should be used.">;
45
46def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
47        "Is32on64bit",
48        "false",
49        "Specify if 64bit sized pointers with 32bit addressing should be used.">;
50
51def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
52        "R600ALUInst",
53        "false",
54        "Older version of ALU instructions encoding.">;
55
56def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
57        "HasVertexCache",
58        "true",
59        "Specify use of dedicated vertex cache.">;
60
61def FeatureCaymanISA : SubtargetFeature<"caymanISA",
62        "CaymanISA",
63        "true",
64        "Use Cayman ISA">;
65
66def FeatureCFALUBug : SubtargetFeature<"cfalubug",
67        "CFALUBug",
68        "true",
69        "GPU has CF_ALU bug">;
70
71class SubtargetFeatureFetchLimit <string Value> :
72                          SubtargetFeature <"fetch"#Value,
73        "TexVTXClauseSize",
74        Value,
75        "Limit the maximum number of fetches in a clause to "#Value>;
76
77def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
78def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
79
80class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
81        "wavefrontsize"#Value,
82        "WavefrontSize",
83        !cast<string>(Value),
84        "The number of threads per wavefront">;
85
86def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
87def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
88def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
89
90class SubtargetFeatureGeneration <string Value,
91                                  list<SubtargetFeature> Implies> :
92        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
93                          Value#" GPU generation", Implies>;
94
95def FeatureR600 : SubtargetFeatureGeneration<"R600",
96        [FeatureR600ALUInst, FeatureFetchLimit8]>;
97
98def FeatureR700 : SubtargetFeatureGeneration<"R700",
99        [FeatureFetchLimit16]>;
100
101def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
102        [FeatureFetchLimit16]>;
103
104def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
105        [FeatureFetchLimit16, FeatureWavefrontSize64]>;
106
107def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
108        [Feature64BitPtr, FeatureFP64]>;
109
110def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
111        [Feature64BitPtr, FeatureFP64]>;
112//===----------------------------------------------------------------------===//
113
114def AMDGPUInstrInfo : InstrInfo {
115  let guessInstructionProperties = 1;
116}
117
118def AMDGPU : Target {
119  // Pull in Instruction Info:
120  let InstructionSet = AMDGPUInstrInfo;
121}
122
123//===----------------------------------------------------------------------===//
124// Predicate helper class
125//===----------------------------------------------------------------------===//
126
127class PredicateControl {
128  Predicate SubtargetPredicate;
129  list<Predicate> OtherPredicates = [];
130  list<Predicate> Predicates = !listconcat([SubtargetPredicate],
131                                            OtherPredicates);
132}
133
134// Include AMDGPU TD files
135include "R600Schedule.td"
136include "SISchedule.td"
137include "Processors.td"
138include "AMDGPUInstrInfo.td"
139include "AMDGPUIntrinsics.td"
140include "AMDGPURegisterInfo.td"
141include "AMDGPUInstructions.td"
142include "AMDGPUCallingConv.td"
143