AMDGPUFrameLowering.cpp revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//===----------------------- AMDGPUFrameLowering.cpp ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9//
10// Interface to describe a layout of a stack frame on a AMDIL target machine
11//
12//===----------------------------------------------------------------------===//
13#include "AMDGPUFrameLowering.h"
14#include "AMDGPURegisterInfo.h"
15#include "R600MachineFunctionInfo.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Instructions.h"
19
20using namespace llvm;
21AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, unsigned StackAl,
22    int LAO, unsigned TransAl)
23  : TargetFrameLowering(D, StackAl, LAO, TransAl) { }
24
25AMDGPUFrameLowering::~AMDGPUFrameLowering() { }
26
27unsigned AMDGPUFrameLowering::getStackWidth(const MachineFunction &MF) const {
28
29  // XXX: Hardcoding to 1 for now.
30  //
31  // I think the StackWidth should stored as metadata associated with the
32  // MachineFunction.  This metadata can either be added by a frontend, or
33  // calculated by a R600 specific LLVM IR pass.
34  //
35  // The StackWidth determines how stack objects are laid out in memory.
36  // For a vector stack variable, like: int4 stack[2], the data will be stored
37  // in the following ways depending on the StackWidth.
38  //
39  // StackWidth = 1:
40  //
41  // T0.X = stack[0].x
42  // T1.X = stack[0].y
43  // T2.X = stack[0].z
44  // T3.X = stack[0].w
45  // T4.X = stack[1].x
46  // T5.X = stack[1].y
47  // T6.X = stack[1].z
48  // T7.X = stack[1].w
49  //
50  // StackWidth = 2:
51  //
52  // T0.X = stack[0].x
53  // T0.Y = stack[0].y
54  // T1.X = stack[0].z
55  // T1.Y = stack[0].w
56  // T2.X = stack[1].x
57  // T2.Y = stack[1].y
58  // T3.X = stack[1].z
59  // T3.Y = stack[1].w
60  //
61  // StackWidth = 4:
62  // T0.X = stack[0].x
63  // T0.Y = stack[0].y
64  // T0.Z = stack[0].z
65  // T0.W = stack[0].w
66  // T1.X = stack[1].x
67  // T1.Y = stack[1].y
68  // T1.Z = stack[1].z
69  // T1.W = stack[1].w
70  return 1;
71}
72
73/// \returns The number of registers allocated for \p FI.
74int AMDGPUFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
75                                         int FI) const {
76  const MachineFrameInfo *MFI = MF.getFrameInfo();
77  // Start the offset at 2 so we don't overwrite work group information.
78  // XXX: We should only do this when the shader actually uses this
79  // information.
80  unsigned OffsetBytes = 2 * (getStackWidth(MF) * 4);
81  int UpperBound = FI == -1 ? MFI->getNumObjects() : FI;
82
83  for (int i = MFI->getObjectIndexBegin(); i < UpperBound; ++i) {
84    OffsetBytes = RoundUpToAlignment(OffsetBytes, MFI->getObjectAlignment(i));
85    OffsetBytes += MFI->getObjectSize(i);
86    // Each register holds 4 bytes, so we must always align the offset to at
87    // least 4 bytes, so that 2 frame objects won't share the same register.
88    OffsetBytes = RoundUpToAlignment(OffsetBytes, 4);
89  }
90
91  if (FI != -1)
92    OffsetBytes = RoundUpToAlignment(OffsetBytes, MFI->getObjectAlignment(FI));
93
94  return OffsetBytes / (getStackWidth(MF) * 4);
95}
96
97const TargetFrameLowering::SpillSlot *
98AMDGPUFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
99  NumEntries = 0;
100  return nullptr;
101}
102void
103AMDGPUFrameLowering::emitPrologue(MachineFunction &MF) const {
104}
105void
106AMDGPUFrameLowering::emitEpilogue(MachineFunction &MF,
107                                  MachineBasicBlock &MBB) const {
108}
109
110bool
111AMDGPUFrameLowering::hasFP(const MachineFunction &MF) const {
112  return false;
113}
114