AMDGPUISelLowering.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition of the TargetLowering class that is common
12/// to all AMD GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef AMDGPUISELLOWERING_H
17#define AMDGPUISELLOWERING_H
18
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class AMDGPUSubtarget;
25class MachineRegisterInfo;
26
27class AMDGPUTargetLowering : public TargetLowering {
28protected:
29  const AMDGPUSubtarget *Subtarget;
30
31private:
32  void ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
33                             SmallVectorImpl<SDValue> &Args,
34                             unsigned Start, unsigned Count) const;
35  SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
36                                   const SDValue &InitPtr,
37                                   SDValue Chain,
38                                   SelectionDAG &DAG) const;
39  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
40  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
41  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
42  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
43  /// \brief Lower vector stores by merging the vector elements into an integer
44  /// of the same bitwidth.
45  SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
46  /// \brief Split a vector store into multiple scalar stores.
47  /// \returns The resulting chain.
48  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
49  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
50
51protected:
52
53  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
54  /// MachineFunction.
55  ///
56  /// \returns a RegisterSDNode representing Reg.
57  virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
58                                       const TargetRegisterClass *RC,
59                                       unsigned Reg, EVT VT) const;
60  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
61                             SelectionDAG &DAG) const;
62  /// \brief Split a vector load into multiple scalar loads.
63  SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
64  SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
65  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
66  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
67  bool isHWTrueValue(SDValue Op) const;
68  bool isHWFalseValue(SDValue Op) const;
69
70  /// The SelectionDAGBuilder will automatically promote function arguments
71  /// with illegal types.  However, this does not work for the AMDGPU targets
72  /// since the function arguments are stored in memory as these illegal types.
73  /// In order to handle this properly we need to get the origianl types sizes
74  /// from the LLVM IR Function and fixup the ISD:InputArg values before
75  /// passing them to AnalyzeFormalArguments()
76  void getOriginalFunctionArgs(SelectionDAG &DAG,
77                               const Function *F,
78                               const SmallVectorImpl<ISD::InputArg> &Ins,
79                               SmallVectorImpl<ISD::InputArg> &OrigIns) const;
80  void AnalyzeFormalArguments(CCState &State,
81                              const SmallVectorImpl<ISD::InputArg> &Ins) const;
82
83public:
84  AMDGPUTargetLowering(TargetMachine &TM);
85
86  virtual bool isFAbsFree(EVT VT) const override;
87  virtual bool isFNegFree(EVT VT) const override;
88  virtual bool isTruncateFree(EVT Src, EVT Dest) const override;
89  virtual bool isTruncateFree(Type *Src, Type *Dest) const override;
90
91  virtual bool isZExtFree(Type *Src, Type *Dest) const override;
92  virtual bool isZExtFree(EVT Src, EVT Dest) const override;
93
94  virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
95
96  virtual MVT getVectorIdxTy() const override;
97  virtual bool isLoadBitCastBeneficial(EVT, EVT) const override;
98  virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
99                              bool isVarArg,
100                              const SmallVectorImpl<ISD::OutputArg> &Outs,
101                              const SmallVectorImpl<SDValue> &OutVals,
102                              SDLoc DL, SelectionDAG &DAG) const;
103  virtual SDValue LowerCall(CallLoweringInfo &CLI,
104                            SmallVectorImpl<SDValue> &InVals) const {
105    CLI.Callee.dump();
106    llvm_unreachable("Undefined function");
107  }
108
109  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
110  virtual void ReplaceNodeResults(SDNode * N,
111                                  SmallVectorImpl<SDValue> &Results,
112                                  SelectionDAG &DAG) const override;
113
114  SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
115  SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
116  SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
117  virtual const char* getTargetNodeName(unsigned Opcode) const;
118
119  virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
120    return N;
121  }
122
123  /// \brief Determine which of the bits specified in \p Mask are known to be
124  /// either zero or one and return them in the \p KnownZero and \p KnownOne
125  /// bitsets.
126  virtual void computeMaskedBitsForTargetNode(const SDValue Op,
127                                              APInt &KnownZero,
128                                              APInt &KnownOne,
129                                              const SelectionDAG &DAG,
130                                              unsigned Depth = 0) const override;
131
132// Functions defined in AMDILISelLowering.cpp
133public:
134  virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
135                                  const CallInst &I, unsigned Intrinsic) const;
136
137  /// We want to mark f32/f64 floating point values as legal.
138  bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
139
140  /// We don't want to shrink f64/f32 constants.
141  bool ShouldShrinkFPConstant(EVT VT) const;
142
143private:
144  void InitAMDILLowering();
145  SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
146  SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
147  SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
148  SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
149  SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
150  SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
151  SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
152  SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
153  SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
154
155  SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
156                                  unsigned BitsDiff,
157                                  SelectionDAG &DAG) const;
158  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
159  EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
160  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
161  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
162};
163
164namespace AMDGPUISD {
165
166enum {
167  // AMDIL ISD Opcodes
168  FIRST_NUMBER = ISD::BUILTIN_OP_END,
169  CALL,        // Function call based on a single integer
170  UMUL,        // 32bit unsigned multiplication
171  DIV_INF,      // Divide with infinity returned on zero divisor
172  RET_FLAG,
173  BRANCH_COND,
174  // End AMDIL ISD Opcodes
175  DWORDADDR,
176  FRACT,
177  COS_HW,
178  SIN_HW,
179  FMAX,
180  SMAX,
181  UMAX,
182  FMIN,
183  SMIN,
184  UMIN,
185  URECIP,
186  DOT4,
187  BFE_U32, // Extract range of bits with zero extension to 32-bits.
188  BFE_I32, // Extract range of bits with sign extension to 32-bits.
189  BFI, // (src0 & src1) | (~src0 & src2)
190  BFM, // Insert a range of bits into a 32-bit word.
191  TEXTURE_FETCH,
192  EXPORT,
193  CONST_ADDRESS,
194  REGISTER_LOAD,
195  REGISTER_STORE,
196  LOAD_INPUT,
197  SAMPLE,
198  SAMPLEB,
199  SAMPLED,
200  SAMPLEL,
201  FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
202  STORE_MSKOR,
203  LOAD_CONSTANT,
204  TBUFFER_STORE_FORMAT,
205  LAST_AMDGPU_ISD_NUMBER
206};
207
208
209} // End namespace AMDGPUISD
210
211} // End namespace llvm
212
213#endif // AMDGPUISELLOWERING_H
214