AMDGPUISelLowering.h revision 509a492442b7e889d615d3b451629c81a810aef1
1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10/// \file 11/// \brief Interface definition of the TargetLowering class that is common 12/// to all AMD GPUs. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef AMDGPUISELLOWERING_H 17#define AMDGPUISELLOWERING_H 18 19#include "llvm/Target/TargetLowering.h" 20 21namespace llvm { 22 23class AMDGPUMachineFunction; 24class MachineRegisterInfo; 25 26class AMDGPUTargetLowering : public TargetLowering { 27private: 28 void ExtractVectorElements(SDValue Op, SelectionDAG &DAG, 29 SmallVectorImpl<SDValue> &Args, 30 unsigned Start, unsigned Count) const; 31 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const; 32 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 33 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 34 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 35 /// \brief Lower vector stores by merging the vector elements into an integer 36 /// of the same bitwidth. 37 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const; 38 /// \brief Split a vector store into multiple scalar stores. 39 /// \returns The resulting chain. 40 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 41 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 42 43protected: 44 45 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's 46 /// MachineFunction. 47 /// 48 /// \returns a RegisterSDNode representing Reg. 49 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, 50 const TargetRegisterClass *RC, 51 unsigned Reg, EVT VT) const; 52 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 53 SelectionDAG &DAG) const; 54 /// \brief Split a vector load into multiple scalar loads. 55 SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const; 56 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const; 57 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 58 bool isHWTrueValue(SDValue Op) const; 59 bool isHWFalseValue(SDValue Op) const; 60 61 /// The SelectionDAGBuilder will automatically promote function arguments 62 /// with illegal types. However, this does not work for the AMDGPU targets 63 /// since the function arguments are stored in memory as these illegal types. 64 /// In order to handle this properly we need to get the origianl types sizes 65 /// from the LLVM IR Function and fixup the ISD:InputArg values before 66 /// passing them to AnalyzeFormalArguments() 67 void getOriginalFunctionArgs(SelectionDAG &DAG, 68 const Function *F, 69 const SmallVectorImpl<ISD::InputArg> &Ins, 70 SmallVectorImpl<ISD::InputArg> &OrigIns) const; 71 void AnalyzeFormalArguments(CCState &State, 72 const SmallVectorImpl<ISD::InputArg> &Ins) const; 73 74public: 75 AMDGPUTargetLowering(TargetMachine &TM); 76 77 virtual bool isFAbsFree(EVT VT) const; 78 virtual bool isFNegFree(EVT VT) const; 79 virtual MVT getVectorIdxTy() const; 80 virtual bool isLoadBitCastBeneficial(EVT, EVT) const LLVM_OVERRIDE; 81 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, 82 bool isVarArg, 83 const SmallVectorImpl<ISD::OutputArg> &Outs, 84 const SmallVectorImpl<SDValue> &OutVals, 85 SDLoc DL, SelectionDAG &DAG) const; 86 virtual SDValue LowerCall(CallLoweringInfo &CLI, 87 SmallVectorImpl<SDValue> &InVals) const { 88 CLI.Callee.dump(); 89 llvm_unreachable("Undefined function"); 90 } 91 92 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 93 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; 94 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; 95 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const; 96 virtual const char* getTargetNodeName(unsigned Opcode) const; 97 98 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const { 99 return N; 100 } 101 102// Functions defined in AMDILISelLowering.cpp 103public: 104 105 /// \brief Determine which of the bits specified in \p Mask are known to be 106 /// either zero or one and return them in the \p KnownZero and \p KnownOne 107 /// bitsets. 108 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 109 APInt &KnownZero, 110 APInt &KnownOne, 111 const SelectionDAG &DAG, 112 unsigned Depth = 0) const; 113 114 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 115 const CallInst &I, unsigned Intrinsic) const; 116 117 /// We want to mark f32/f64 floating point values as legal. 118 bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 119 120 /// We don't want to shrink f64/f32 constants. 121 bool ShouldShrinkFPConstant(EVT VT) const; 122 123private: 124 void InitAMDILLowering(); 125 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const; 126 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const; 127 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const; 128 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const; 129 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const; 130 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const; 131 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const; 132 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const; 133 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const; 134 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 135 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const; 136 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 137 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 138}; 139 140namespace AMDGPUISD { 141 142enum { 143 // AMDIL ISD Opcodes 144 FIRST_NUMBER = ISD::BUILTIN_OP_END, 145 CALL, // Function call based on a single integer 146 UMUL, // 32bit unsigned multiplication 147 DIV_INF, // Divide with infinity returned on zero divisor 148 RET_FLAG, 149 BRANCH_COND, 150 // End AMDIL ISD Opcodes 151 DWORDADDR, 152 FRACT, 153 COS_HW, 154 SIN_HW, 155 FMAX, 156 SMAX, 157 UMAX, 158 FMIN, 159 SMIN, 160 UMIN, 161 URECIP, 162 DOT4, 163 TEXTURE_FETCH, 164 EXPORT, 165 CONST_ADDRESS, 166 REGISTER_LOAD, 167 REGISTER_STORE, 168 LOAD_INPUT, 169 SAMPLE, 170 SAMPLEB, 171 SAMPLED, 172 SAMPLEL, 173 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE, 174 STORE_MSKOR, 175 LOAD_CONSTANT, 176 TBUFFER_STORE_FORMAT, 177 LAST_AMDGPU_ISD_NUMBER 178}; 179 180 181} // End namespace AMDGPUISD 182 183} // End namespace llvm 184 185#endif // AMDGPUISELLOWERING_H 186