AMDGPUISelLowering.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition of the TargetLowering class that is common
12/// to all AMD GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef AMDGPUISELLOWERING_H
17#define AMDGPUISELLOWERING_H
18
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class AMDGPUSubtarget;
25class MachineRegisterInfo;
26
27class AMDGPUTargetLowering : public TargetLowering {
28protected:
29  const AMDGPUSubtarget *Subtarget;
30
31private:
32  SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33                                   const SDValue &InitPtr,
34                                   SDValue Chain,
35                                   SelectionDAG &DAG) const;
36  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40  /// \brief Lower vector stores by merging the vector elements into an integer
41  /// of the same bitwidth.
42  SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43  /// \brief Split a vector store into multiple scalar stores.
44  /// \returns The resulting chain.
45  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
46  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
47
48protected:
49
50  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
51  /// MachineFunction.
52  ///
53  /// \returns a RegisterSDNode representing Reg.
54  virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
55                                       const TargetRegisterClass *RC,
56                                       unsigned Reg, EVT VT) const;
57  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
58                             SelectionDAG &DAG) const;
59  /// \brief Split a vector load into multiple scalar loads.
60  SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
61  SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
62  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
63  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
64  bool isHWTrueValue(SDValue Op) const;
65  bool isHWFalseValue(SDValue Op) const;
66
67  /// The SelectionDAGBuilder will automatically promote function arguments
68  /// with illegal types.  However, this does not work for the AMDGPU targets
69  /// since the function arguments are stored in memory as these illegal types.
70  /// In order to handle this properly we need to get the origianl types sizes
71  /// from the LLVM IR Function and fixup the ISD:InputArg values before
72  /// passing them to AnalyzeFormalArguments()
73  void getOriginalFunctionArgs(SelectionDAG &DAG,
74                               const Function *F,
75                               const SmallVectorImpl<ISD::InputArg> &Ins,
76                               SmallVectorImpl<ISD::InputArg> &OrigIns) const;
77  void AnalyzeFormalArguments(CCState &State,
78                              const SmallVectorImpl<ISD::InputArg> &Ins) const;
79
80public:
81  AMDGPUTargetLowering(TargetMachine &TM);
82
83  bool isFAbsFree(EVT VT) const override;
84  bool isFNegFree(EVT VT) const override;
85  bool isTruncateFree(EVT Src, EVT Dest) const override;
86  bool isTruncateFree(Type *Src, Type *Dest) const override;
87
88  bool isZExtFree(Type *Src, Type *Dest) const override;
89  bool isZExtFree(EVT Src, EVT Dest) const override;
90
91  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
92
93  MVT getVectorIdxTy() const override;
94  bool isLoadBitCastBeneficial(EVT, EVT) const override;
95  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
96                      bool isVarArg,
97                      const SmallVectorImpl<ISD::OutputArg> &Outs,
98                      const SmallVectorImpl<SDValue> &OutVals,
99                      SDLoc DL, SelectionDAG &DAG) const override;
100  SDValue LowerCall(CallLoweringInfo &CLI,
101                    SmallVectorImpl<SDValue> &InVals) const override;
102
103  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
104  void ReplaceNodeResults(SDNode * N,
105                          SmallVectorImpl<SDValue> &Results,
106                          SelectionDAG &DAG) const override;
107
108  SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
109  SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
110  SDValue CombineMinMax(SDNode *N, SelectionDAG &DAG) const;
111  const char* getTargetNodeName(unsigned Opcode) const override;
112
113  virtual SDNode *PostISelFolding(MachineSDNode *N,
114                                  SelectionDAG &DAG) const {
115    return N;
116  }
117
118  /// \brief Determine which of the bits specified in \p Mask are known to be
119  /// either zero or one and return them in the \p KnownZero and \p KnownOne
120  /// bitsets.
121  void computeKnownBitsForTargetNode(const SDValue Op,
122                                     APInt &KnownZero,
123                                     APInt &KnownOne,
124                                     const SelectionDAG &DAG,
125                                     unsigned Depth = 0) const override;
126
127  virtual unsigned ComputeNumSignBitsForTargetNode(
128    SDValue Op,
129    const SelectionDAG &DAG,
130    unsigned Depth = 0) const override;
131
132// Functions defined in AMDILISelLowering.cpp
133public:
134  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
135                          const CallInst &I, unsigned Intrinsic) const override;
136
137  /// We want to mark f32/f64 floating point values as legal.
138  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
139
140  /// We don't want to shrink f64/f32 constants.
141  bool ShouldShrinkFPConstant(EVT VT) const override;
142
143  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
144
145private:
146  void InitAMDILLowering();
147  SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
148  SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
149  SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
150  SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
151  SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
152  SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
153  SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
154  SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
155  SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
156
157  SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
158                                  unsigned BitsDiff,
159                                  SelectionDAG &DAG) const;
160  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
161  EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
162  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
163};
164
165namespace AMDGPUISD {
166
167enum {
168  // AMDIL ISD Opcodes
169  FIRST_NUMBER = ISD::BUILTIN_OP_END,
170  CALL,        // Function call based on a single integer
171  UMUL,        // 32bit unsigned multiplication
172  DIV_INF,      // Divide with infinity returned on zero divisor
173  RET_FLAG,
174  BRANCH_COND,
175  // End AMDIL ISD Opcodes
176  DWORDADDR,
177  FRACT,
178  COS_HW,
179  SIN_HW,
180  FMAX,
181  SMAX,
182  UMAX,
183  FMIN,
184  SMIN,
185  UMIN,
186  URECIP,
187  DOT4,
188  BFE_U32, // Extract range of bits with zero extension to 32-bits.
189  BFE_I32, // Extract range of bits with sign extension to 32-bits.
190  BFI, // (src0 & src1) | (~src0 & src2)
191  BFM, // Insert a range of bits into a 32-bit word.
192  MUL_U24,
193  MUL_I24,
194  MAD_U24,
195  MAD_I24,
196  TEXTURE_FETCH,
197  EXPORT,
198  CONST_ADDRESS,
199  REGISTER_LOAD,
200  REGISTER_STORE,
201  LOAD_INPUT,
202  SAMPLE,
203  SAMPLEB,
204  SAMPLED,
205  SAMPLEL,
206  FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
207  STORE_MSKOR,
208  LOAD_CONSTANT,
209  TBUFFER_STORE_FORMAT,
210  LAST_AMDGPU_ISD_NUMBER
211};
212
213
214} // End namespace AMDGPUISD
215
216} // End namespace llvm
217
218#endif // AMDGPUISELLOWERING_H
219