1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===// 2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// The LLVM Compiler Infrastructure 4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source 6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details. 7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \file 11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \brief Implementation of the TargetInstrInfo class that is common to all 12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// AMD GPUs. 13f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 14f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 15f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 16f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUInstrInfo.h" 17f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPURegisterInfo.h" 18f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUTargetMachine.h" 19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineFrameInfo.h" 20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineInstrBuilder.h" 21f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineRegisterInfo.h" 22f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 23dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesusing namespace llvm; 24dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 25354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka#define GET_INSTRINFO_CTOR_DTOR 265e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0Tom Stellard#define GET_INSTRINFO_NAMED_OPS 27f767018b1048f228b0c2a71d7e4008750aff0ef5Christian Konig#define GET_INSTRMAP_INFO 28f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUGenInstrInfo.inc" 29f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 30354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka// Pin the vtable to this file. 31354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzkavoid AMDGPUInstrInfo::anchor() {} 32354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka 33cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen HinesAMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &st) 34cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines : AMDGPUGenInstrInfo(-1,-1), RI(st), ST(st) { } 35f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 36f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardconst AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { 37f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return RI; 38f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 39f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 40f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 41f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned &SrcReg, unsigned &DstReg, 42f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned &SubIdx) const { 43f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 44f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 45f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 46f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 47f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 48f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 49f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 50f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 51f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 52f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 53f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 54f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 55f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 56f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 57f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 58f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 59f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 60f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MachineMemOperand *&MMO, 61f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 62f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 63f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 64f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 65f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, 66f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 67f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 68f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 69f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 70f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, 71f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 72f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 73f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 74f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 75f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, 76f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MachineMemOperand *&MMO, 77f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 78f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 79f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 80f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 81f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 82f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr * 83f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 84f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator &MBBI, 85f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard LiveVariables *LV) const { 86f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 87dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 88f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 89f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter, 90f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock &MBB) const { 91f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard while (iter != MBB.end()) { 92f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard switch (iter->getOpcode()) { 93f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard default: 94f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard break; 95f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH_COND_i32: 96f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH_COND_f32: 97f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH: 98f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 99f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard }; 100f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard ++iter; 101f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 102f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 103f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 104f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 105f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid 106f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 107f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI, 108f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned SrcReg, bool isKill, 109f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int FrameIndex, 110f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass *RC, 111f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterInfo *TRI) const { 11236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines llvm_unreachable("Not Implemented"); 113f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 114f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 115f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid 116f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 117f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI, 118f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned DestReg, int FrameIndex, 119f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass *RC, 120f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterInfo *TRI) const { 12136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines llvm_unreachable("Not Implemented"); 122f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 123f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 12404c559569f87d755c3f2828a765f5eb7308e6753Tom Stellardbool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const { 12504c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard MachineBasicBlock *MBB = MI->getParent(); 12636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 12736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines AMDGPU::OpName::addr); 128a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard // addr is a custom operand with multiple MI operands, and only the 129a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard // first MI operand is given a name. 130a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int RegOpIdx = OffsetOpIdx + 1; 13136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 13236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines AMDGPU::OpName::chan); 1335203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman if (isRegisterLoad(*MI)) { 13436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 13536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines AMDGPU::OpName::dst); 136a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); 137a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned Channel = MI->getOperand(ChanOpIdx).getImm(); 1385203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman unsigned Address = calculateIndirectAddress(RegIndex, Channel); 139a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg(); 1405203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { 141a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(), 1425203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman getIndirectAddrRegClass()->getRegister(Address)); 14304c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard } else { 144a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(), 1455203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman Address, OffsetReg); 14604c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard } 1475203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman } else if (isRegisterStore(*MI)) { 14836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 14936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines AMDGPU::OpName::val); 150a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); 151a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); 152a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned Channel = MI->getOperand(ChanOpIdx).getImm(); 1535203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman unsigned Address = calculateIndirectAddress(RegIndex, Channel); 154a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg(); 1555203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { 1565203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address), 157a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard MI->getOperand(ValOpIdx).getReg()); 1585203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman } else { 159a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(), 160a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard calculateIndirectAddress(RegIndex, Channel), 161a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard OffsetReg); 1625203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman } 1635203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman } else { 1645203b7773e29b36e38aac0ce9358fa7843065681Aaron Ballman return false; 16504c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard } 16604c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard 16704c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard MBB->erase(MI); 16804c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard return true; 16904c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard} 17004c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard 17104c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard 172f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr * 173f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 174f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *MI, 175f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops, 176f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int FrameIndex) const { 177f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 178dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 179f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 180f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr* 181f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 182f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *MI, 183f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops, 184f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *LoadMI) const { 185f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 186dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 187f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 188f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 189f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 190f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops) const { 191f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 192f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 193f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 194f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 195f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 196f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned Reg, bool UnfoldLoad, 197f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool UnfoldStore, 198f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard SmallVectorImpl<MachineInstr*> &NewMIs) const { 199f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 200f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 201f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 202f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 203f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 204f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 205f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard SmallVectorImpl<SDNode*> &NewNodes) const { 206f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 207f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 208f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 209f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 210f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned 211f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 212f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool UnfoldLoad, bool UnfoldStore, 213f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned *LoadRegIndex) const { 214f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 215f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 216f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 217f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 218f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 219f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int64_t Offset1, int64_t Offset2, 220f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned NumLoads) const { 221f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(Offset2 > Offset1 222f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard && "Second offset should be larger than first offset!"); 223f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // If we have less than 16 loads in a row, and the offsets are within 16, 224f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // then schedule together. 225f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Make the loads schedule near if it fits in a cacheline 226f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return (NumLoads < 16 && (Offset2 - Offset1) < 16); 227f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 228f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 229f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 230f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) 231f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const { 232f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 233f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 234f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 235f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB, 236f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI) const { 237f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 238f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 239f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 240f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { 241f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 242f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 243f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 244f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 245f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 246f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<MachineOperand> &Pred2) 247f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const { 248f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 249f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 250f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 251f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 252f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI, 253f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard std::vector<MachineOperand> &Pred) const { 254f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 255f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 256f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 257f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 258f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const { 259f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 260f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return MI->getDesc().isPredicable(); 261f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 262f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 263f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 264f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 265f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 266f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 267f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 268c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 269c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellardbool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const { 270c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE; 271c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard} 272c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 273c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellardbool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const { 274c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD; 275c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard} 276c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 277a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellardint AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const { 278a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard const MachineRegisterInfo &MRI = MF.getRegInfo(); 279a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard const MachineFrameInfo *MFI = MF.getFrameInfo(); 280a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int Offset = -1; 281a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 282a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (MFI->getNumObjects() == 0) { 283a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return -1; 284a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 285a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 286a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (MRI.livein_empty()) { 287a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return 0; 288a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 289a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 290a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass(); 291a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 292a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard LE = MRI.livein_end(); 293a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard LI != LE; ++LI) { 294a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned Reg = LI->first; 295a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (TargetRegisterInfo::isVirtualRegister(Reg) || 296a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard !IndirectRC->contains(Reg)) 297a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard continue; 298a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 299a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned RegIndex; 300a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard unsigned RegEnd; 301a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; 302a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard ++RegIndex) { 303a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (IndirectRC->getRegister(RegIndex) == Reg) 304a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard break; 305a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 306a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard Offset = std::max(Offset, (int)RegIndex); 307a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 308a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 309a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return Offset + 1; 310a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard} 311a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 312a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellardint AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const { 313a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard int Offset = 0; 314a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard const MachineFrameInfo *MFI = MF.getFrameInfo(); 315a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 316a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard // Variable sized objects are not supported 317a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard assert(!MFI->hasVarSizedObjects()); 318a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 319a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard if (MFI->getNumObjects() == 0) { 320a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return -1; 321a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard } 322a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 323cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines Offset = MF.getTarget().getFrameLowering()->getFrameIndexOffset(MF, -1); 324a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 325a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard return getIndirectIndexBegin(MF) + Offset; 326a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard} 327a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 3280f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellardint AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const { 3290f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard switch (Channels) { 3300f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard default: return Opcode; 3310f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1); 3320f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2); 3330f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3); 3340f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard } 3350f9eaaa8aa10bdb658e887782b86f03dbea79cb1Tom Stellard} 336dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 337dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// Wrapper for Tablegen'd function. enum Subtarget is not defined in any 338dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// header files, so we need to wrap it in a function that takes unsigned 339dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// instead. 340dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesnamespace llvm { 341dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesnamespace AMDGPU { 342dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesint getMCOpcode(uint16_t Opcode, unsigned Gen) { 343dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return getMCOpcode(Opcode); 344dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 345dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 346dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 347