AMDGPUInstrInfo.cpp revision 5b00e833fabbf5bdf2973c63c39d4a0d0143853a
1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===// 2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// The LLVM Compiler Infrastructure 4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source 6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details. 7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \file 11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \brief Implementation of the TargetInstrInfo class that is common to all 12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// AMD GPUs. 13f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 14f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 15f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 16f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUInstrInfo.h" 17f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPURegisterInfo.h" 18f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUTargetMachine.h" 19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineFrameInfo.h" 20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineInstrBuilder.h" 21f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/CodeGen/MachineRegisterInfo.h" 22f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 23f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#define GET_INSTRINFO_CTOR 245e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0Tom Stellard#define GET_INSTRINFO_NAMED_OPS 25f767018b1048f228b0c2a71d7e4008750aff0ef5Christian Konig#define GET_INSTRMAP_INFO 26f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUGenInstrInfo.inc" 27f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 28f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardusing namespace llvm; 29f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 30f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) 315b00e833fabbf5bdf2973c63c39d4a0d0143853aVincent Lejeune : AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { } 32f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 33f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardconst AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { 34f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return RI; 35f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 36f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 37f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 38f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned &SrcReg, unsigned &DstReg, 39f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned &SubIdx) const { 40f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 41f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 42f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 43f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 44f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 45f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 46f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 47f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 48f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 49f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 50f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 51f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 52f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 53f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 54f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 55f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 56f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 57f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MachineMemOperand *&MMO, 58f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 59f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 60f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 61f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 62f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, 63f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 64f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 65f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 66f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 67f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, 68f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 69f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 70f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 71f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 72f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, 73f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MachineMemOperand *&MMO, 74f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int &FrameIndex) const { 75f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 76f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 77f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 78f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 79f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr * 80f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 81f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator &MBBI, 82f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard LiveVariables *LV) const { 83f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 84f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return NULL; 85f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 86f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter, 87f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock &MBB) const { 88f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard while (iter != MBB.end()) { 89f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard switch (iter->getOpcode()) { 90f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard default: 91f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard break; 92f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH_COND_i32: 93f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH_COND_f32: 94f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::BRANCH: 95f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 96f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard }; 97f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard ++iter; 98f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 99f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 100f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 101f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 102f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid 103f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 104f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI, 105f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned SrcReg, bool isKill, 106f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int FrameIndex, 107f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass *RC, 108f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterInfo *TRI) const { 109f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(!"Not Implemented"); 110f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 111f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 112f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid 113f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 114f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI, 115f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned DestReg, int FrameIndex, 116f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass *RC, 117f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterInfo *TRI) const { 118f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(!"Not Implemented"); 119f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 120f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 121f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr * 122f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 123f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *MI, 124f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops, 125f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int FrameIndex) const { 126f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// TODO: Implement this function 127f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 128f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 129f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardMachineInstr* 130f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 131f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *MI, 132f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops, 133f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *LoadMI) const { 134f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 135f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 136f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 137f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 138f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 139f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<unsigned> &Ops) const { 140f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 141f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 142f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 143f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 144f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 145f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned Reg, bool UnfoldLoad, 146f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool UnfoldStore, 147f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard SmallVectorImpl<MachineInstr*> &NewMIs) const { 148f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 149f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 150f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 151f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 152f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 153f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 154f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard SmallVectorImpl<SDNode*> &NewNodes) const { 155f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 156f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 157f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 158f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 159f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardunsigned 160f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 161f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool UnfoldLoad, bool UnfoldStore, 162f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned *LoadRegIndex) const { 163f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 164f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return 0; 165f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 166f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 167f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 168f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard int64_t Offset1, int64_t Offset2, 169f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned NumLoads) const { 170f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(Offset2 > Offset1 171f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard && "Second offset should be larger than first offset!"); 172f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // If we have less than 16 loads in a row, and the offsets are within 16, 173f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // then schedule together. 174f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Make the loads schedule near if it fits in a cacheline 175f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return (NumLoads < 16 && (Offset2 - Offset1) < 16); 176f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 177f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 178f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 179f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) 180f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const { 181f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 182f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 183f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 184f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB, 185f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator MI) const { 186f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 187f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 188f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 189f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { 190f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 191f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 192f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 193f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 194f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 195f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const SmallVectorImpl<MachineOperand> &Pred2) 196f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const { 197f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 198f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 199f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 200f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 201f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI, 202f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard std::vector<MachineOperand> &Pred) const { 203f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 204f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return false; 205f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 206f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 207f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const { 208f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 209f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return MI->getDesc().isPredicable(); 210f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 211f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 212f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardbool 213f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardAMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 214f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // TODO: Implement this function 215f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return true; 216f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 217c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 218c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellardbool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const { 219c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE; 220c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard} 221c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 222c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellardbool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const { 223c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD; 224c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard} 225c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 226c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 227f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF, 228f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard DebugLoc DL) const { 229f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineRegisterInfo &MRI = MF.getRegInfo(); 230f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const AMDGPURegisterInfo & RI = getRegisterInfo(); 231f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 232f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard for (unsigned i = 0; i < MI.getNumOperands(); i++) { 233f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineOperand &MO = MI.getOperand(i); 234f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // Convert dst regclass to one that is supported by the ISA 235f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (MO.isReg() && MO.isDef()) { 236f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 237f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); 238f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass); 239f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 240f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(newRegClass); 241f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 242f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MRI.setRegClass(MO.getReg(), newRegClass); 243f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 244f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 245f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 246f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 247