AMDGPUInstrInfo.h revision 354362524a72b3fa43a6c09380b7ae3b2380cbba
1//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10/// \file 11/// \brief Contains the definition of a TargetInstrInfo class that is common 12/// to all AMD GPUs. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef AMDGPUINSTRUCTIONINFO_H 17#define AMDGPUINSTRUCTIONINFO_H 18 19#include "AMDGPUInstrInfo.h" 20#include "AMDGPURegisterInfo.h" 21#include "llvm/Target/TargetInstrInfo.h" 22#include <map> 23 24#define GET_INSTRINFO_HEADER 25#define GET_INSTRINFO_ENUM 26#define GET_INSTRINFO_OPERAND_ENUM 27#include "AMDGPUGenInstrInfo.inc" 28 29#define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT 30#define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT 31#define OPCODE_IS_ZERO AMDGPU::PRED_SETE 32#define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE 33 34namespace llvm { 35 36class AMDGPUTargetMachine; 37class MachineFunction; 38class MachineInstr; 39class MachineInstrBuilder; 40 41class AMDGPUInstrInfo : public AMDGPUGenInstrInfo { 42private: 43 const AMDGPURegisterInfo RI; 44 bool getNextBranchInstr(MachineBasicBlock::iterator &iter, 45 MachineBasicBlock &MBB) const; 46 virtual void anchor(); 47protected: 48 TargetMachine &TM; 49public: 50 explicit AMDGPUInstrInfo(TargetMachine &tm); 51 52 virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0; 53 54 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 55 unsigned &DstReg, unsigned &SubIdx) const; 56 57 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 58 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 59 int &FrameIndex) const; 60 bool hasLoadFromStackSlot(const MachineInstr *MI, 61 const MachineMemOperand *&MMO, 62 int &FrameIndex) const; 63 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 64 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, 65 int &FrameIndex) const; 66 bool hasStoreFromStackSlot(const MachineInstr *MI, 67 const MachineMemOperand *&MMO, 68 int &FrameIndex) const; 69 70 MachineInstr * 71 convertToThreeAddress(MachineFunction::iterator &MFI, 72 MachineBasicBlock::iterator &MBBI, 73 LiveVariables *LV) const; 74 75 76 virtual void copyPhysReg(MachineBasicBlock &MBB, 77 MachineBasicBlock::iterator MI, DebugLoc DL, 78 unsigned DestReg, unsigned SrcReg, 79 bool KillSrc) const = 0; 80 81 void storeRegToStackSlot(MachineBasicBlock &MBB, 82 MachineBasicBlock::iterator MI, 83 unsigned SrcReg, bool isKill, int FrameIndex, 84 const TargetRegisterClass *RC, 85 const TargetRegisterInfo *TRI) const; 86 void loadRegFromStackSlot(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator MI, 88 unsigned DestReg, int FrameIndex, 89 const TargetRegisterClass *RC, 90 const TargetRegisterInfo *TRI) const; 91 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 92 93 94protected: 95 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, 96 MachineInstr *MI, 97 const SmallVectorImpl<unsigned> &Ops, 98 int FrameIndex) const; 99 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, 100 MachineInstr *MI, 101 const SmallVectorImpl<unsigned> &Ops, 102 MachineInstr *LoadMI) const; 103 /// \returns the smallest register index that will be accessed by an indirect 104 /// read or write or -1 if indirect addressing is not used by this program. 105 virtual int getIndirectIndexBegin(const MachineFunction &MF) const; 106 107 /// \returns the largest register index that will be accessed by an indirect 108 /// read or write or -1 if indirect addressing is not used by this program. 109 virtual int getIndirectIndexEnd(const MachineFunction &MF) const; 110 111public: 112 bool canFoldMemoryOperand(const MachineInstr *MI, 113 const SmallVectorImpl<unsigned> &Ops) const; 114 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 115 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 116 SmallVectorImpl<MachineInstr *> &NewMIs) const; 117 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 118 SmallVectorImpl<SDNode *> &NewNodes) const; 119 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 120 bool UnfoldLoad, bool UnfoldStore, 121 unsigned *LoadRegIndex = 0) const; 122 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 123 int64_t Offset1, int64_t Offset2, 124 unsigned NumLoads) const; 125 126 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 127 void insertNoop(MachineBasicBlock &MBB, 128 MachineBasicBlock::iterator MI) const; 129 bool isPredicated(const MachineInstr *MI) const; 130 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 131 const SmallVectorImpl<MachineOperand> &Pred2) const; 132 bool DefinesPredicate(MachineInstr *MI, 133 std::vector<MachineOperand> &Pred) const; 134 bool isPredicable(MachineInstr *MI) const; 135 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 136 137 // Helper functions that check the opcode for status information 138 bool isLoadInst(llvm::MachineInstr *MI) const; 139 bool isExtLoadInst(llvm::MachineInstr *MI) const; 140 bool isSWSExtLoadInst(llvm::MachineInstr *MI) const; 141 bool isSExtLoadInst(llvm::MachineInstr *MI) const; 142 bool isZExtLoadInst(llvm::MachineInstr *MI) const; 143 bool isAExtLoadInst(llvm::MachineInstr *MI) const; 144 bool isStoreInst(llvm::MachineInstr *MI) const; 145 bool isTruncStoreInst(llvm::MachineInstr *MI) const; 146 bool isRegisterStore(const MachineInstr &MI) const; 147 bool isRegisterLoad(const MachineInstr &MI) const; 148 149//===---------------------------------------------------------------------===// 150// Pure virtual funtions to be implemented by sub-classes. 151//===---------------------------------------------------------------------===// 152 153 virtual unsigned getIEQOpcode() const = 0; 154 virtual bool isMov(unsigned opcode) const = 0; 155 156 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and 157 /// \p Channel 158 /// 159 /// We model indirect addressing using a virtual address space that can be 160 /// accesed with loads and stores. The "Indirect Address" is the memory 161 /// address in this virtual address space that maps to the given \p RegIndex 162 /// and \p Channel. 163 virtual unsigned calculateIndirectAddress(unsigned RegIndex, 164 unsigned Channel) const = 0; 165 166 /// \returns The register class to be used for loading and storing values 167 /// from an "Indirect Address" . 168 virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0; 169 170 /// \brief Build instruction(s) for an indirect register write. 171 /// 172 /// \returns The instruction that performs the indirect register write 173 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 174 MachineBasicBlock::iterator I, 175 unsigned ValueReg, unsigned Address, 176 unsigned OffsetReg) const = 0; 177 178 /// \brief Build instruction(s) for an indirect register read. 179 /// 180 /// \returns The instruction that performs the indirect register read 181 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 182 MachineBasicBlock::iterator I, 183 unsigned ValueReg, unsigned Address, 184 unsigned OffsetReg) const = 0; 185 186 187 /// \brief Convert the AMDIL MachineInstr to a supported ISA 188 /// MachineInstr 189 virtual void convertToISA(MachineInstr & MI, MachineFunction &MF, 190 DebugLoc DL) const; 191 192 /// \brief Build a MOV instruction. 193 virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB, 194 MachineBasicBlock::iterator I, 195 unsigned DstReg, unsigned SrcReg) const = 0; 196 197 /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the 198 /// equivalent opcode that writes \p Channels Channels. 199 int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const; 200 201}; 202 203namespace AMDGPU { 204 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 205} // End namespace AMDGPU 206 207} // End llvm namespace 208 209#define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63) 210#define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62) 211 212#endif // AMDGPUINSTRINFO_H 213