AMDGPUInstrInfo.h revision a2b4eb6d15a13de257319ac6231b5ab622cd02b1 
1//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Contains the definition of a TargetInstrInfo class that is common
12/// to all AMD GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef AMDGPUINSTRUCTIONINFO_H
17#define AMDGPUINSTRUCTIONINFO_H
18
19#include "AMDGPUInstrInfo.h"
20#include "AMDGPURegisterInfo.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include <map>
23
24#define GET_INSTRINFO_HEADER
25#define GET_INSTRINFO_ENUM
26#define GET_INSTRINFO_OPERAND_ENUM
27#include "AMDGPUGenInstrInfo.inc"
28
29#define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
30#define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
31#define OPCODE_IS_ZERO AMDGPU::PRED_SETE
32#define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
33
34namespace llvm {
35
36class AMDGPUTargetMachine;
37class MachineFunction;
38class MachineInstr;
39class MachineInstrBuilder;
40
41class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
42private:
43  const AMDGPURegisterInfo RI;
44  bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
45                          MachineBasicBlock &MBB) const;
46protected:
47  TargetMachine &TM;
48public:
49  explicit AMDGPUInstrInfo(TargetMachine &tm);
50
51  virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
52
53  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54                             unsigned &DstReg, unsigned &SubIdx) const;
55
56  unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
57  unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
58                                     int &FrameIndex) const;
59  bool hasLoadFromStackSlot(const MachineInstr *MI,
60                            const MachineMemOperand *&MMO,
61                            int &FrameIndex) const;
62  unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
63  unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
64                                      int &FrameIndex) const;
65  bool hasStoreFromStackSlot(const MachineInstr *MI,
66                             const MachineMemOperand *&MMO,
67                             int &FrameIndex) const;
68
69  MachineInstr *
70  convertToThreeAddress(MachineFunction::iterator &MFI,
71                        MachineBasicBlock::iterator &MBBI,
72                        LiveVariables *LV) const;
73
74
75  virtual void copyPhysReg(MachineBasicBlock &MBB,
76                           MachineBasicBlock::iterator MI, DebugLoc DL,
77                           unsigned DestReg, unsigned SrcReg,
78                           bool KillSrc) const = 0;
79
80  void storeRegToStackSlot(MachineBasicBlock &MBB,
81                           MachineBasicBlock::iterator MI,
82                           unsigned SrcReg, bool isKill, int FrameIndex,
83                           const TargetRegisterClass *RC,
84                           const TargetRegisterInfo *TRI) const;
85  void loadRegFromStackSlot(MachineBasicBlock &MBB,
86                            MachineBasicBlock::iterator MI,
87                            unsigned DestReg, int FrameIndex,
88                            const TargetRegisterClass *RC,
89                            const TargetRegisterInfo *TRI) const;
90  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
91
92
93protected:
94  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
95                                      MachineInstr *MI,
96                                      const SmallVectorImpl<unsigned> &Ops,
97                                      int FrameIndex) const;
98  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
99                                      MachineInstr *MI,
100                                      const SmallVectorImpl<unsigned> &Ops,
101                                      MachineInstr *LoadMI) const;
102  /// \returns the smallest register index that will be accessed by an indirect
103  /// read or write or -1 if indirect addressing is not used by this program.
104  virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
105
106  /// \returns the largest register index that will be accessed by an indirect
107  /// read or write or -1 if indirect addressing is not used by this program.
108  virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
109
110public:
111  bool canFoldMemoryOperand(const MachineInstr *MI,
112                            const SmallVectorImpl<unsigned> &Ops) const;
113  bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
114                           unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
115                           SmallVectorImpl<MachineInstr *> &NewMIs) const;
116  bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
117                           SmallVectorImpl<SDNode *> &NewNodes) const;
118  unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
119                                      bool UnfoldLoad, bool UnfoldStore,
120                                      unsigned *LoadRegIndex = 0) const;
121  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
122                               int64_t Offset1, int64_t Offset2,
123                               unsigned NumLoads) const;
124
125  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
126  void insertNoop(MachineBasicBlock &MBB,
127                  MachineBasicBlock::iterator MI) const;
128  bool isPredicated(const MachineInstr *MI) const;
129  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
130                         const SmallVectorImpl<MachineOperand> &Pred2) const;
131  bool DefinesPredicate(MachineInstr *MI,
132                        std::vector<MachineOperand> &Pred) const;
133  bool isPredicable(MachineInstr *MI) const;
134  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
135
136  // Helper functions that check the opcode for status information
137  bool isLoadInst(llvm::MachineInstr *MI) const;
138  bool isExtLoadInst(llvm::MachineInstr *MI) const;
139  bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
140  bool isSExtLoadInst(llvm::MachineInstr *MI) const;
141  bool isZExtLoadInst(llvm::MachineInstr *MI) const;
142  bool isAExtLoadInst(llvm::MachineInstr *MI) const;
143  bool isStoreInst(llvm::MachineInstr *MI) const;
144  bool isTruncStoreInst(llvm::MachineInstr *MI) const;
145  bool isRegisterStore(const MachineInstr &MI) const;
146  bool isRegisterLoad(const MachineInstr &MI) const;
147
148//===---------------------------------------------------------------------===//
149// Pure virtual funtions to be implemented by sub-classes.
150//===---------------------------------------------------------------------===//
151
152  virtual unsigned getIEQOpcode() const = 0;
153  virtual bool isMov(unsigned opcode) const = 0;
154
155  /// \brief Calculate the "Indirect Address" for the given \p RegIndex and
156  ///        \p Channel
157  ///
158  /// We model indirect addressing using a virtual address space that can be
159  /// accesed with loads and stores.  The "Indirect Address" is the memory
160  /// address in this virtual address space that maps to the given \p RegIndex
161  /// and \p Channel.
162  virtual unsigned calculateIndirectAddress(unsigned RegIndex,
163                                            unsigned Channel) const = 0;
164
165  /// \returns The register class to be used for loading and storing values
166  /// from an "Indirect Address" .
167  virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0;
168
169  /// \brief Build instruction(s) for an indirect register write.
170  ///
171  /// \returns The instruction that performs the indirect register write
172  virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
173                                    MachineBasicBlock::iterator I,
174                                    unsigned ValueReg, unsigned Address,
175                                    unsigned OffsetReg) const = 0;
176
177  /// \brief Build instruction(s) for an indirect register read.
178  ///
179  /// \returns The instruction that performs the indirect register read
180  virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
181                                    MachineBasicBlock::iterator I,
182                                    unsigned ValueReg, unsigned Address,
183                                    unsigned OffsetReg) const = 0;
184
185
186  /// \brief Convert the AMDIL MachineInstr to a supported ISA
187  /// MachineInstr
188  virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
189    DebugLoc DL) const;
190
191  /// \brief Build a MOV instruction.
192  virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
193                                      MachineBasicBlock::iterator I,
194                                      unsigned DstReg, unsigned SrcReg) const = 0;
195
196  /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
197  /// equivalent opcode that writes \p Channels Channels.
198  int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
199
200};
201
202namespace AMDGPU {
203  int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
204}  // End namespace AMDGPU
205
206} // End llvm namespace
207
208#define AMDGPU_FLAG_REGISTER_LOAD  (UINT64_C(1) << 63)
209#define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
210
211#endif // AMDGPUINSTRINFO_H
212