AMDGPUInstrInfo.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains DAG node defintions for the AMDGPU target.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// AMDGPU DAG Profiles
16//===----------------------------------------------------------------------===//
17
18def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
20]>;
21
22//===----------------------------------------------------------------------===//
23// AMDGPU DAG Nodes
24//
25
26// This argument to this node is a dword address.
27def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
28
29// out = a - floor(a)
30def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
31
32// out = max(a, b) a and b are floats
33def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
34  [SDNPCommutative, SDNPAssociative]
35>;
36
37// out = max(a, b) a and b are signed ints
38def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
39  [SDNPCommutative, SDNPAssociative]
40>;
41
42// out = max(a, b) a and b are unsigned ints
43def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
44  [SDNPCommutative, SDNPAssociative]
45>;
46
47// out = min(a, b) a and b are floats
48def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
49  [SDNPCommutative, SDNPAssociative]
50>;
51
52// out = min(a, b) a snd b are signed ints
53def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
54  [SDNPCommutative, SDNPAssociative]
55>;
56
57// out = min(a, b) a and b are unsigned ints
58def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
59  [SDNPCommutative, SDNPAssociative]
60>;
61
62// urecip - This operation is a helper for integer division, it returns the
63// result of 1 / a as a fractional unsigned integer.
64// out = (2^32 / a) + e
65// e is rounding error
66def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
67
68def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
69                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
70                          [SDNPHasChain, SDNPMayLoad]>;
71
72def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
73                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
74                           [SDNPHasChain, SDNPMayStore]>;
75
76// MSKOR instructions are atomic memory instructions used mainly for storing
77// 8-bit and 16-bit values.  The definition is:
78//
79// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
80//
81// src0: vec4(src, 0, 0, mask)
82// src1: dst - rat offset (aka pointer) in dwords  
83def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
84                        SDTypeProfile<0, 2, []>,
85                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
86
87def AMDGPUround : SDNode<"ISD::FROUND",
88                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
89
90def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
91def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
92def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
93def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
94
95