AMDGPUInstrInfo.td revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains DAG node defintions for the AMDGPU target.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// AMDGPU DAG Profiles
16//===----------------------------------------------------------------------===//
17
18def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
20]>;
21
22def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
24>;
25
26def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
27  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
28>;
29
30//===----------------------------------------------------------------------===//
31// AMDGPU DAG Nodes
32//
33
34// This argument to this node is a dword address.
35def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
36
37// out = a - floor(a)
38def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
39
40// out = 1.0 / a
41def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
42
43// out = 1.0 / sqrt(a)
44def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
45
46// out = 1.0 / sqrt(a)
47def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
48
49// out = 1.0 / sqrt(a) result clamped to +/- max_float.
50def AMDGPUrsq_clamped : SDNode<"AMDGPUISD::RSQ_CLAMPED", SDTFPUnaryOp>;
51
52// out = max(a, b) a and b are floats
53def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
54  [SDNPCommutative, SDNPAssociative]
55>;
56
57def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
58
59// out = max(a, b) a and b are signed ints
60def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
61  [SDNPCommutative, SDNPAssociative]
62>;
63
64// out = max(a, b) a and b are unsigned ints
65def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
66  [SDNPCommutative, SDNPAssociative]
67>;
68
69// out = min(a, b) a and b are floats
70def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
71  [SDNPCommutative, SDNPAssociative]
72>;
73
74// out = min(a, b) a snd b are signed ints
75def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
76  [SDNPCommutative, SDNPAssociative]
77>;
78
79// out = min(a, b) a and b are unsigned ints
80def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
81  [SDNPCommutative, SDNPAssociative]
82>;
83
84
85def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
86  SDTIntToFPOp, []>;
87def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
88  SDTIntToFPOp, []>;
89def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
90  SDTIntToFPOp, []>;
91def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
92  SDTIntToFPOp, []>;
93
94
95// urecip - This operation is a helper for integer division, it returns the
96// result of 1 / a as a fractional unsigned integer.
97// out = (2^32 / a) + e
98// e is rounding error
99def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
100
101// Special case divide preop and flags.
102def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
103
104//  Special case divide FMA with scale and flags (src0 = Quotient,
105//  src1 = Denominator, src2 = Numerator).
106def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", SDTFPTernaryOp>;
107
108// Single or double precision division fixup.
109// Special case divide fixup and flags(src0 = Quotient, src1 =
110// Denominator, src2 = Numerator).
111def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
112
113// Look Up 2.0 / pi src0 with segment select src1[4:0]
114def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
115
116def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
117                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
118                          [SDNPHasChain, SDNPMayLoad]>;
119
120def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
121                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
122                           [SDNPHasChain, SDNPMayStore]>;
123
124// MSKOR instructions are atomic memory instructions used mainly for storing
125// 8-bit and 16-bit values.  The definition is:
126//
127// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
128//
129// src0: vec4(src, 0, 0, mask)
130// src1: dst - rat offset (aka pointer) in dwords  
131def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
132                        SDTypeProfile<0, 2, []>,
133                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134
135def AMDGPUround : SDNode<"ISD::FROUND",
136                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
137
138def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
139def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
140def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
141def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
142
143def AMDGPUbrev : SDNode<"AMDGPUISD::BREV", SDTIntUnaryOp>;
144
145// Signed and unsigned 24-bit mulitply.  The highest 8-bits are ignore when
146// performing the mulitply.  The result is a 32-bit value.
147def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
148  [SDNPCommutative]
149>;
150def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
151  [SDNPCommutative]
152>;
153
154def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
155  []
156>;
157def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
158  []
159>;
160
161//===----------------------------------------------------------------------===//
162// Flow Control Profile Types
163//===----------------------------------------------------------------------===//
164// Branch instruction where second and third are basic blocks
165def SDTIL_BRCond : SDTypeProfile<0, 2, [
166    SDTCisVT<0, OtherVT>
167    ]>;
168
169//===----------------------------------------------------------------------===//
170// Flow Control DAG Nodes
171//===----------------------------------------------------------------------===//
172def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
173
174//===----------------------------------------------------------------------===//
175// Call/Return DAG Nodes
176//===----------------------------------------------------------------------===//
177def IL_retflag       : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
178    [SDNPHasChain, SDNPOptInGlue]>;
179