AMDGPUIntrinsics.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===-- AMDGPUIntrinsics.td - Common intrinsics -*- tablegen -*-----------===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file defines intrinsics that are used by all hw codegen targets. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 14eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdochlet TargetPrefix = "AMDGPU", isTarget = 1 in { 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>; 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>; 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>; 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>; 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>; 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>; 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>; 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_kilp : Intrinsic<[], [], []>; 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_lrp : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_mul : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_pow : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_rcp : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_rsq : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_seq : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_sgt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_sge : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_sle : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_sne : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_mullit : Intrinsic<[llvm_v4f32_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_tex : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_txb : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_trunc : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_imax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_imin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_umul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_imul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_imad24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_umad24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; 575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_bfi : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_bfe_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_bfe_u32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_bfm : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_AMDGPU_barrier_local : Intrinsic<[], [], []>; 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)let TargetPrefix = "TGSI", isTarget = 1 in { 655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def int_TGSI_lit_z : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],[IntrNoMem]>; 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)include "SIIntrinsics.td" 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)