AMDGPUMCInstLower.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
12//
13//===----------------------------------------------------------------------===//
14//
15
16#include "AMDGPUMCInstLower.h"
17#include "AMDGPUAsmPrinter.h"
18#include "InstPrinter/AMDGPUInstPrinter.h"
19#include "R600InstrInfo.h"
20#include "SIInstrInfo.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/IR/Constants.h"
24#include "llvm/MC/MCCodeEmitter.h"
25#include "llvm/MC/MCExpr.h"
26#include "llvm/MC/MCInst.h"
27#include "llvm/MC/MCObjectStreamer.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/Format.h"
31#include <algorithm>
32
33using namespace llvm;
34
35AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
36  Ctx(ctx), ST(st)
37{ }
38
39enum AMDGPUMCInstLower::SISubtarget
40AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned) const {
41  return AMDGPUMCInstLower::SI;
42}
43
44unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {
45
46  int MCOpcode = AMDGPU::getMCOpcode(MIOpcode,
47                              AMDGPUSubtargetToSISubtarget(ST.getGeneration()));
48  if (MCOpcode == -1)
49    MCOpcode = MIOpcode;
50
51  return MCOpcode;
52}
53
54void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
55
56  OutMI.setOpcode(getMCOpcode(MI->getOpcode()));
57
58  for (const MachineOperand &MO : MI->explicit_operands()) {
59    MCOperand MCOp;
60    switch (MO.getType()) {
61    default:
62      llvm_unreachable("unknown operand type");
63    case MachineOperand::MO_FPImmediate: {
64      const APFloat &FloatValue = MO.getFPImm()->getValueAPF();
65      assert(&FloatValue.getSemantics() == &APFloat::IEEEsingle &&
66             "Only floating point immediates are supported at the moment.");
67      MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
68      break;
69    }
70    case MachineOperand::MO_Immediate:
71      MCOp = MCOperand::CreateImm(MO.getImm());
72      break;
73    case MachineOperand::MO_Register:
74      MCOp = MCOperand::CreateReg(MO.getReg());
75      break;
76    case MachineOperand::MO_MachineBasicBlock:
77      MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
78                                   MO.getMBB()->getSymbol(), Ctx));
79    }
80    OutMI.addOperand(MCOp);
81  }
82}
83
84void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
85  AMDGPUMCInstLower MCInstLowering(OutContext,
86                               MF->getTarget().getSubtarget<AMDGPUSubtarget>());
87
88#ifdef _DEBUG
89  StringRef Err;
90  if (!TM.getInstrInfo()->verifyInstruction(MI, Err)) {
91    errs() << "Warning: Illegal instruction detected: " << Err << "\n";
92    MI->dump();
93  }
94#endif
95  if (MI->isBundle()) {
96    const MachineBasicBlock *MBB = MI->getParent();
97    MachineBasicBlock::const_instr_iterator I = MI;
98    ++I;
99    while (I != MBB->end() && I->isInsideBundle()) {
100      EmitInstruction(I);
101      ++I;
102    }
103  } else {
104    MCInst TmpInst;
105    MCInstLowering.lower(MI, TmpInst);
106    EmitToStreamer(OutStreamer, TmpInst);
107
108    if (DisasmEnabled) {
109      // Disassemble instruction/operands to text.
110      DisasmLines.resize(DisasmLines.size() + 1);
111      std::string &DisasmLine = DisasmLines.back();
112      raw_string_ostream DisasmStream(DisasmLine);
113
114      AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *TM.getInstrInfo(),
115                                    *TM.getRegisterInfo());
116      InstPrinter.printInst(&TmpInst, DisasmStream, StringRef());
117
118      // Disassemble instruction/operands to hex representation.
119      SmallVector<MCFixup, 4> Fixups;
120      SmallVector<char, 16> CodeBytes;
121      raw_svector_ostream CodeStream(CodeBytes);
122
123      MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer;
124      MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
125      InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
126                                    TM.getSubtarget<MCSubtargetInfo>());
127      CodeStream.flush();
128
129      HexLines.resize(HexLines.size() + 1);
130      std::string &HexLine = HexLines.back();
131      raw_string_ostream HexStream(HexLine);
132
133      for (size_t i = 0; i < CodeBytes.size(); i += 4) {
134        unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
135        HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
136      }
137
138      DisasmStream.flush();
139      DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
140    }
141  }
142}
143