AMDGPURegisterInfo.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPURegisterInfo.h"
16#include "AMDGPUTargetMachine.h"
17
18using namespace llvm;
19
20AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm)
21: AMDGPUGenRegisterInfo(0),
22  TM(tm)
23  { }
24
25//===----------------------------------------------------------------------===//
26// Function handling callbacks - Functions are a seldom used feature of GPUS, so
27// they are not supported at this time.
28//===----------------------------------------------------------------------===//
29
30const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
31
32const MCPhysReg*
33AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
34  return &CalleeSavedReg;
35}
36
37void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
38                                             int SPAdj,
39                                             unsigned FIOperandNum,
40                                             RegScavenger *RS) const {
41  llvm_unreachable("Subroutines not supported yet");
42}
43
44unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
45  assert(!"Subroutines not supported yet");
46  return 0;
47}
48
49unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
50  static const unsigned SubRegs[] = {
51    AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
52    AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
53    AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
54    AMDGPU::sub15
55  };
56
57  assert(Channel < array_lengthof(SubRegs));
58  return SubRegs[Channel];
59}
60
61unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
62
63  return getSubRegFromChannel(IndirectIndex);
64}
65
66#define GET_REGINFO_TARGET_DESC
67#include "AMDGPUGenRegisterInfo.inc"
68