1//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief The AMDGPU target machine contains all of the hardware specific
12/// information  needed to emit code for R600 and SI GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#include "AMDGPUTargetMachine.h"
17#include "AMDGPU.h"
18#include "R600ISelLowering.h"
19#include "R600InstrInfo.h"
20#include "R600MachineScheduler.h"
21#include "SIISelLowering.h"
22#include "SIInstrInfo.h"
23#include "llvm/Analysis/Passes.h"
24#include "llvm/CodeGen/MachineFunctionAnalysis.h"
25#include "llvm/CodeGen/MachineModuleInfo.h"
26#include "llvm/CodeGen/Passes.h"
27#include "llvm/IR/Verifier.h"
28#include "llvm/MC/MCAsmInfo.h"
29#include "llvm/PassManager.h"
30#include "llvm/Support/TargetRegistry.h"
31#include "llvm/Support/raw_os_ostream.h"
32#include "llvm/Transforms/IPO.h"
33#include "llvm/Transforms/Scalar.h"
34#include <llvm/CodeGen/Passes.h>
35
36
37using namespace llvm;
38
39extern "C" void LLVMInitializeR600Target() {
40  // Register the target
41  RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
42}
43
44static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
45  return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
46}
47
48static MachineSchedRegistry
49SchedCustomRegistry("r600", "Run R600's custom scheduler",
50                    createR600MachineScheduler);
51
52static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
53  std::string Ret = "e-p:32:32";
54
55  if (ST.is64bit()) {
56    // 32-bit private, local, and region pointers. 64-bit global and constant.
57    Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
58  }
59
60  Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
61         "-v512:512-v1024:1024-v2048:2048-n32:64";
62
63  return Ret;
64}
65
66AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
67    StringRef CPU, StringRef FS,
68  TargetOptions Options,
69  Reloc::Model RM, CodeModel::Model CM,
70  CodeGenOpt::Level OptLevel
71)
72:
73  LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
74  Subtarget(TT, CPU, FS),
75  Layout(computeDataLayout(Subtarget)),
76  FrameLowering(TargetFrameLowering::StackGrowsUp,
77                64 * 16 // Maximum stack alignment (long16)
78               , 0),
79  IntrinsicInfo(this),
80  InstrItins(&Subtarget.getInstrItineraryData()) {
81  // TLInfo uses InstrInfo so it must be initialized after.
82  if (Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
83    TLInfo.reset(new R600TargetLowering(*this));
84  } else {
85    TLInfo.reset(new SITargetLowering(*this));
86  }
87  setRequiresStructuredCFG(true);
88  initAsmInfo();
89}
90
91AMDGPUTargetMachine::~AMDGPUTargetMachine() {
92}
93
94namespace {
95class AMDGPUPassConfig : public TargetPassConfig {
96public:
97  AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
98    : TargetPassConfig(TM, PM) {}
99
100  AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
101    return getTM<AMDGPUTargetMachine>();
102  }
103
104  ScheduleDAGInstrs *
105  createMachineScheduler(MachineSchedContext *C) const override {
106    const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
107    if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
108      return createR600MachineScheduler(C);
109    return nullptr;
110  }
111
112  virtual void addCodeGenPrepare();
113  bool addPreISel() override;
114  bool addInstSelector() override;
115  bool addPreRegAlloc() override;
116  bool addPostRegAlloc() override;
117  bool addPreSched2() override;
118  bool addPreEmitPass() override;
119};
120} // End of anonymous namespace
121
122TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
123  return new AMDGPUPassConfig(this, PM);
124}
125
126//===----------------------------------------------------------------------===//
127// AMDGPU Analysis Pass Setup
128//===----------------------------------------------------------------------===//
129
130void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
131  // Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
132  // allows the AMDGPU pass to delegate to the target independent layer when
133  // appropriate.
134  PM.add(createBasicTargetTransformInfoPass(this));
135  PM.add(createAMDGPUTargetTransformInfoPass(this));
136}
137
138void AMDGPUPassConfig::addCodeGenPrepare() {
139  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
140  addPass(createAMDGPUPromoteAlloca(ST));
141  addPass(createSROAPass());
142  TargetPassConfig::addCodeGenPrepare();
143}
144
145bool
146AMDGPUPassConfig::addPreISel() {
147  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
148  addPass(createFlattenCFGPass());
149  if (ST.IsIRStructurizerEnabled())
150    addPass(createStructurizeCFGPass());
151  if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
152    addPass(createSinkingPass());
153    addPass(createSITypeRewriter());
154    addPass(createSIAnnotateControlFlowPass());
155  } else {
156    addPass(createR600TextureIntrinsicsReplacer());
157  }
158  return false;
159}
160
161bool AMDGPUPassConfig::addInstSelector() {
162  addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
163  addPass(createSILowerI1CopiesPass());
164  return false;
165}
166
167bool AMDGPUPassConfig::addPreRegAlloc() {
168  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
169
170  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
171    addPass(createR600VectorRegMerger(*TM));
172  } else {
173    addPass(createSIFixSGPRCopiesPass(*TM));
174    // SIFixSGPRCopies can generate a lot of duplicate instructions,
175    // so we need to run MachineCSE afterwards.
176    addPass(&MachineCSEID);
177    initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry());
178    insertPass(&RegisterCoalescerID, &SIFixSGPRLiveRangesID);
179  }
180  return false;
181}
182
183bool AMDGPUPassConfig::addPostRegAlloc() {
184  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
185
186  if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
187    addPass(createSIInsertWaits(*TM));
188  }
189  return false;
190}
191
192bool AMDGPUPassConfig::addPreSched2() {
193  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
194
195  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
196    addPass(createR600EmitClauseMarkers());
197  if (ST.isIfCvtEnabled())
198    addPass(&IfConverterID);
199  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
200    addPass(createR600ClauseMergePass(*TM));
201  return false;
202}
203
204bool AMDGPUPassConfig::addPreEmitPass() {
205  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
206  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
207    addPass(createAMDGPUCFGStructurizerPass());
208    addPass(createR600ExpandSpecialInstrsPass(*TM));
209    addPass(&FinalizeMachineBundlesID);
210    addPass(createR600Packetizer(*TM));
211    addPass(createR600ControlFlowFinalizer(*TM));
212  } else {
213    addPass(createSILowerControlFlowPass(*TM));
214  }
215
216  return false;
217}
218