AMDGPUTargetMachine.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief The AMDGPU target machine contains all of the hardware specific
12/// information  needed to emit code for R600 and SI GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#include "AMDGPUTargetMachine.h"
17#include "AMDGPU.h"
18#include "R600ISelLowering.h"
19#include "R600InstrInfo.h"
20#include "R600MachineScheduler.h"
21#include "SIISelLowering.h"
22#include "SIInstrInfo.h"
23#include "llvm/Analysis/Passes.h"
24#include "llvm/CodeGen/MachineFunctionAnalysis.h"
25#include "llvm/CodeGen/MachineModuleInfo.h"
26#include "llvm/CodeGen/Passes.h"
27#include "llvm/IR/Verifier.h"
28#include "llvm/MC/MCAsmInfo.h"
29#include "llvm/PassManager.h"
30#include "llvm/Support/TargetRegistry.h"
31#include "llvm/Support/raw_os_ostream.h"
32#include "llvm/Transforms/IPO.h"
33#include "llvm/Transforms/Scalar.h"
34#include <llvm/CodeGen/Passes.h>
35
36
37using namespace llvm;
38
39extern "C" void LLVMInitializeR600Target() {
40  // Register the target
41  RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
42}
43
44static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
45  return new ScheduleDAGMILive(C, new R600SchedStrategy());
46}
47
48static MachineSchedRegistry
49SchedCustomRegistry("r600", "Run R600's custom scheduler",
50                    createR600MachineScheduler);
51
52static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
53  std::string Ret = "e-p:32:32";
54
55  if (ST.is64bit()) {
56    // 32-bit private, local, and region pointers. 64-bit global and constant.
57    Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64";
58  }
59
60  Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
61         "-v512:512-v1024:1024-v2048:2048-n32:64";
62
63  return Ret;
64}
65
66AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
67    StringRef CPU, StringRef FS,
68  TargetOptions Options,
69  Reloc::Model RM, CodeModel::Model CM,
70  CodeGenOpt::Level OptLevel
71)
72:
73  LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
74  Subtarget(TT, CPU, FS),
75  Layout(computeDataLayout(Subtarget)),
76  FrameLowering(TargetFrameLowering::StackGrowsUp,
77                64 * 16 // Maximum stack alignment (long16)
78               , 0),
79  IntrinsicInfo(this),
80  InstrItins(&Subtarget.getInstrItineraryData()) {
81  // TLInfo uses InstrInfo so it must be initialized after.
82  if (Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
83    InstrInfo.reset(new R600InstrInfo(*this));
84    TLInfo.reset(new R600TargetLowering(*this));
85  } else {
86    InstrInfo.reset(new SIInstrInfo(*this));
87    TLInfo.reset(new SITargetLowering(*this));
88  }
89  setRequiresStructuredCFG(true);
90  initAsmInfo();
91}
92
93AMDGPUTargetMachine::~AMDGPUTargetMachine() {
94}
95
96namespace {
97class AMDGPUPassConfig : public TargetPassConfig {
98public:
99  AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
100    : TargetPassConfig(TM, PM) {}
101
102  AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
103    return getTM<AMDGPUTargetMachine>();
104  }
105
106  virtual ScheduleDAGInstrs *
107  createMachineScheduler(MachineSchedContext *C) const {
108    const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
109    if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
110      return createR600MachineScheduler(C);
111    return 0;
112  }
113
114  virtual bool addPreISel();
115  virtual bool addInstSelector();
116  virtual bool addPreRegAlloc();
117  virtual bool addPostRegAlloc();
118  virtual bool addPreSched2();
119  virtual bool addPreEmitPass();
120};
121} // End of anonymous namespace
122
123TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
124  return new AMDGPUPassConfig(this, PM);
125}
126
127//===----------------------------------------------------------------------===//
128// AMDGPU Analysis Pass Setup
129//===----------------------------------------------------------------------===//
130
131void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
132  // Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
133  // allows the AMDGPU pass to delegate to the target independent layer when
134  // appropriate.
135  PM.add(createBasicTargetTransformInfoPass(this));
136  PM.add(createAMDGPUTargetTransformInfoPass(this));
137}
138
139bool
140AMDGPUPassConfig::addPreISel() {
141  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
142  addPass(createFlattenCFGPass());
143  if (ST.IsIRStructurizerEnabled())
144    addPass(createStructurizeCFGPass());
145  if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
146    addPass(createSinkingPass());
147    addPass(createSITypeRewriter());
148    addPass(createSIAnnotateControlFlowPass());
149  } else {
150    addPass(createR600TextureIntrinsicsReplacer());
151  }
152  return false;
153}
154
155bool AMDGPUPassConfig::addInstSelector() {
156  addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
157  return false;
158}
159
160bool AMDGPUPassConfig::addPreRegAlloc() {
161  addPass(createAMDGPUConvertToISAPass(*TM));
162  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
163
164  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
165    addPass(createR600VectorRegMerger(*TM));
166  } else {
167    addPass(createSIFixSGPRCopiesPass(*TM));
168    // SIFixSGPRCopies can generate a lot of duplicate instructions,
169    // so we need to run MachineCSE afterwards.
170    addPass(&MachineCSEID);
171  }
172  return false;
173}
174
175bool AMDGPUPassConfig::addPostRegAlloc() {
176  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
177
178  if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
179    addPass(createSIInsertWaits(*TM));
180  }
181  return false;
182}
183
184bool AMDGPUPassConfig::addPreSched2() {
185  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
186
187  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
188    addPass(createR600EmitClauseMarkers());
189  if (ST.isIfCvtEnabled())
190    addPass(&IfConverterID);
191  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
192    addPass(createR600ClauseMergePass(*TM));
193  return false;
194}
195
196bool AMDGPUPassConfig::addPreEmitPass() {
197  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
198  if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
199    addPass(createAMDGPUCFGStructurizerPass());
200    addPass(createR600ExpandSpecialInstrsPass(*TM));
201    addPass(&FinalizeMachineBundlesID);
202    addPass(createR600Packetizer(*TM));
203    addPass(createR600ControlFlowFinalizer(*TM));
204  } else {
205    addPass(createSILowerControlFlowPass(*TM));
206  }
207
208  return false;
209}
210