1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===// 2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// The LLVM Compiler Infrastructure 4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source 6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details. 7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// \file 9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUInstPrinter.h" 12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "MCTargetDesc/AMDGPUMCTargetDesc.h" 1353f22df199542f6fc4e0edc5b7cecbeacea11adaChristian Konig#include "llvm/MC/MCExpr.h" 145c35290fa35ae234fed02496404cb0fc37e1c8a5Benjamin Kramer#include "llvm/MC/MCInst.h" 15dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "llvm/MC/MCRegisterInfo.h" 16dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "llvm/Support/MathExtras.h" 17f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 18f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardusing namespace llvm; 19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, 21f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard StringRef Annot) { 2292f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune OS.flush(); 23f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard printInstruction(MI, OS); 24f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 25f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard printAnnotation(OS, Annot); 26f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 27f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 28dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesvoid AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, 29dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines raw_ostream &O) { 30dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); 31dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 32dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 33dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesvoid AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, 34dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines raw_ostream &O) { 35dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff); 36dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 37dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 38dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesvoid AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, 39dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines raw_ostream &O) { 40dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); 41dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 42dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 4386245071b52f1da99ac65157c38bfa5577a80714Matt Arsenaultvoid AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) { 4486245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault switch (reg) { 4586245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault case AMDGPU::VCC: 4686245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault O << "vcc"; 4786245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault return; 4886245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault case AMDGPU::SCC: 4986245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault O << "scc"; 5086245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault return; 5186245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault case AMDGPU::EXEC: 5286245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault O << "exec"; 5386245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault return; 5486245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault case AMDGPU::M0: 5586245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault O << "m0"; 5686245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault return; 5786245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault default: 5886245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault break; 5986245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault } 6086245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault 61dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines char Type; 62dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned NumRegs; 63dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 64dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) { 65dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 'v'; 66dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 1; 67dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) { 68dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 's'; 69dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 1; 70dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) { 71dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 'v'; 72dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 2; 73dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) { 74dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 's'; 75dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 2; 76dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) { 77dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 'v'; 78dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 4; 79dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) { 80dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 's'; 81dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 4; 82dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) { 83dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 'v'; 84dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 3; 85dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) { 86dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 'v'; 87dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 8; 88dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) { 89dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 's'; 90dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 8; 91dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) { 92dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 'v'; 93dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 16; 94dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) { 95dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Type = 's'; 96dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumRegs = 16; 97dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } else { 98dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << getRegisterName(reg); 99dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return; 100dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 10186245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault 102cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // The low 8 bits of the encoding value is the register index, for both VGPRs 103cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // and SGPRs. 104cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1); 105dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (NumRegs == 1) { 106dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << Type << RegIdx; 10786245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault return; 10886245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault } 10986245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault 110dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']'; 111dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 11286245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault 113dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesvoid AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) { 114dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int32_t SImm = static_cast<int32_t>(Imm); 115dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (SImm >= -16 && SImm <= 64) { 116dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << SImm; 11786245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault return; 11886245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault } 11986245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault 120dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (Imm == FloatToBits(1.0f) || 121dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Imm == FloatToBits(-1.0f) || 122dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Imm == FloatToBits(0.5f) || 123dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Imm == FloatToBits(-0.5f) || 124dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Imm == FloatToBits(2.0f) || 125dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Imm == FloatToBits(-2.0f) || 126dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Imm == FloatToBits(4.0f) || 127dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Imm == FloatToBits(-4.0f)) { 128dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << BitsToFloat(Imm); 12986245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault return; 13086245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault } 13186245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault 132dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << formatHex(static_cast<uint64_t>(Imm)); 13386245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault} 13486245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault 135f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 136f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 137f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 138f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MCOperand &Op = MI->getOperand(OpNo); 139f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (Op.isReg()) { 140f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard switch (Op.getReg()) { 141f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard // This is the default predicate state, so we don't need to print it. 14286245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault case AMDGPU::PRED_SEL_OFF: 14386245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault break; 14486245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault 14586245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault default: 14686245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault printRegOperand(Op.getReg(), O); 14786245071b52f1da99ac65157c38bfa5577a80714Matt Arsenault break; 148f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 149f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } else if (Op.isImm()) { 150dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines printImmediate(Op.getImm(), O); 151f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } else if (Op.isFPImm()) { 152f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard O << Op.getFPImm(); 15353f22df199542f6fc4e0edc5b7cecbeacea11adaChristian Konig } else if (Op.isExpr()) { 15453f22df199542f6fc4e0edc5b7cecbeacea11adaChristian Konig const MCExpr *Exp = Op.getExpr(); 15553f22df199542f6fc4e0edc5b7cecbeacea11adaChristian Konig Exp->print(O); 156f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } else { 157f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(!"unknown operand type in printOperand"); 158f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 159f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 160f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 161dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesvoid AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo, 162dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines raw_ostream &O) { 163dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned InputModifiers = MI->getOperand(OpNo).getImm(); 164dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (InputModifiers & 0x1) 165dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << "-"; 166dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (InputModifiers & 0x2) 167dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << "|"; 168dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines printOperand(MI, OpNo + 1, O); 169dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (InputModifiers & 0x2) 170dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines O << "|"; 171dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 172dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 17301115b1f5032b848659669b161af1bdd9e646208Michel Danzervoid AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum, 17401115b1f5032b848659669b161af1bdd9e646208Michel Danzer raw_ostream &O) { 17501115b1f5032b848659669b161af1bdd9e646208Michel Danzer unsigned Imm = MI->getOperand(OpNum).getImm(); 17601115b1f5032b848659669b161af1bdd9e646208Michel Danzer 17701115b1f5032b848659669b161af1bdd9e646208Michel Danzer if (Imm == 2) { 17801115b1f5032b848659669b161af1bdd9e646208Michel Danzer O << "P0"; 17901115b1f5032b848659669b161af1bdd9e646208Michel Danzer } else if (Imm == 1) { 18001115b1f5032b848659669b161af1bdd9e646208Michel Danzer O << "P20"; 18101115b1f5032b848659669b161af1bdd9e646208Michel Danzer } else if (Imm == 0) { 18201115b1f5032b848659669b161af1bdd9e646208Michel Danzer O << "P10"; 18301115b1f5032b848659669b161af1bdd9e646208Michel Danzer } else { 18401115b1f5032b848659669b161af1bdd9e646208Michel Danzer assert(!"Invalid interpolation parameter slot"); 18501115b1f5032b848659669b161af1bdd9e646208Michel Danzer } 18601115b1f5032b848659669b161af1bdd9e646208Michel Danzer} 18701115b1f5032b848659669b161af1bdd9e646208Michel Danzer 188f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, 189f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 190f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard printOperand(MI, OpNo, O); 191f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard O << ", "; 192f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard printOperand(MI, OpNo + 1, O); 193f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 194f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 195f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, 19692f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune raw_ostream &O, StringRef Asm, 19792f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune StringRef Default) { 198f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MCOperand &Op = MI->getOperand(OpNo); 199f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard assert(Op.isImm()); 200f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (Op.getImm() == 1) { 201f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard O << Asm; 20292f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune } else { 20392f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune O << Default; 204f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 205f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 206f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 207f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo, 208f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 209f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard printIfSet(MI, OpNo, O, "|"); 210f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 211f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 212f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo, 213f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 214f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard printIfSet(MI, OpNo, O, "_SAT"); 215f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 216f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 217f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo, 218f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 219cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines int32_t Imm = MI->getOperand(OpNo).getImm(); 220cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines O << Imm << '(' << BitsToFloat(Imm) << ')'; 221f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 222f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 223f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo, 224f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 2259a9e936650bb82244f38dbddf6c4e427c2ae49f9Vincent Lejeune printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " "); 226f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 227f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 228f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo, 229f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 230f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard printIfSet(MI, OpNo, O, "-"); 231f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 232f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 233f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo, 234f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 235f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard switch (MI->getOperand(OpNo).getImm()) { 236f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard default: break; 237f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case 1: 238f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard O << " * 2.0"; 239f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard break; 240f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case 2: 241f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard O << " * 4.0"; 242f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard break; 243f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case 3: 244f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard O << " / 2.0"; 245f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard break; 246f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 247f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 248f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 249f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo, 250f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 251c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard printIfSet(MI, OpNo, O, "+"); 252f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 253f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 254f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo, 255f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 256f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard printIfSet(MI, OpNo, O, "ExecMask,"); 257f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 258f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 259f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo, 260f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 261f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard printIfSet(MI, OpNo, O, "Pred,"); 262f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 263f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 264f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardvoid AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo, 265f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &O) { 266f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MCOperand &Op = MI->getOperand(OpNo); 267f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (Op.getImm() == 0) { 268f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard O << " (MASKED)"; 269f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 270f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 271f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 2729f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellardvoid AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo, 2739f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard raw_ostream &O) { 2749f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard const char * chans = "XYZW"; 2759f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard int sel = MI->getOperand(OpNo).getImm(); 2769f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard 2779f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard int chan = sel & 3; 2789f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard sel >>= 2; 2799f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard 2809f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard if (sel >= 512) { 2819f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard sel -= 512; 2829f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard int cb = sel >> 12; 2839f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard sel &= 4095; 2849f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard O << cb << "[" << sel << "]"; 2859f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard } else if (sel >= 448) { 2869f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard sel -= 448; 2879f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard O << sel; 2889f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard } else if (sel >= 0){ 2899f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard O << sel; 2909f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard } 2919f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard 2929f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard if (sel >= 0) 2939f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard O << "." << chans[chan]; 2949f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard} 2959f7818d9bdfce2e9c7a2cbe31490a135aa6d1211Tom Stellard 29692f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeunevoid AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo, 29792f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune raw_ostream &O) { 29892f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune int BankSwizzle = MI->getOperand(OpNo).getImm(); 29992f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune switch (BankSwizzle) { 30092f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune case 1: 3017d1a0d4e3ebf058a8b1d0dea9b6119444ed041c8Vincent Lejeune O << "BS:VEC_021/SCL_122"; 30292f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune break; 30392f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune case 2: 3047d1a0d4e3ebf058a8b1d0dea9b6119444ed041c8Vincent Lejeune O << "BS:VEC_120/SCL_212"; 30592f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune break; 30692f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune case 3: 3077d1a0d4e3ebf058a8b1d0dea9b6119444ed041c8Vincent Lejeune O << "BS:VEC_102/SCL_221"; 30892f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune break; 30992f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune case 4: 31092f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune O << "BS:VEC_201"; 31192f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune break; 31292f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune case 5: 31392f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune O << "BS:VEC_210"; 31492f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune break; 31592f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune default: 31692f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune break; 31792f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune } 31892f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune return; 31992f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune} 32092f24d403f16ab2ee4598e32c926acc9c2344140Vincent Lejeune 321d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeunevoid AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo, 322d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune raw_ostream &O) { 323d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune unsigned Sel = MI->getOperand(OpNo).getImm(); 324d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune switch (Sel) { 325d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune case 0: 326d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune O << "X"; 327d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 328d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune case 1: 329d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune O << "Y"; 330d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 331d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune case 2: 332d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune O << "Z"; 333d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 334d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune case 3: 335d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune O << "W"; 336d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 337d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune case 4: 338d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune O << "0"; 339d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 340d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune case 5: 341d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune O << "1"; 342d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 343d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune case 7: 344d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune O << "_"; 345d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 346d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune default: 347d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 348d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune } 349d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune} 350d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune 351d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeunevoid AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo, 352d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune raw_ostream &O) { 353d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune unsigned CT = MI->getOperand(OpNo).getImm(); 354d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune switch (CT) { 355d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune case 0: 356d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune O << "U"; 357d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 358d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune case 1: 359d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune O << "N"; 360d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 361d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune default: 362d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune break; 363d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune } 364d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune} 365d3293b49f9c7af741d2edd3062499fb50db0e89bVincent Lejeune 3669e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeunevoid AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo, 3679e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune raw_ostream &O) { 3689e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune int KCacheMode = MI->getOperand(OpNo).getImm(); 3699e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune if (KCacheMode > 0) { 3709e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune int KCacheBank = MI->getOperand(OpNo - 2).getImm(); 3719e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune O << "CB" << KCacheBank <<":"; 3729e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune int KCacheAddr = MI->getOperand(OpNo + 2).getImm(); 3739e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune int LineSize = (KCacheMode == 1)?16:32; 3749e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune O << KCacheAddr * 16 << "-" << KCacheAddr * 16 + LineSize; 3759e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune } 3769e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune} 3779e1808733eeea4f248eeef35ba06ee3f7aa5707dVincent Lejeune 37836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesvoid AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo, 37936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines raw_ostream &O) { 38036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned SImm16 = MI->getOperand(OpNo).getImm(); 38136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned Msg = SImm16 & 0xF; 38236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Msg == 2 || Msg == 3) { 38336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned Op = (SImm16 >> 4) & 0xF; 38436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Msg == 3) 38536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "Gs_done("; 38636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines else 38736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "Gs("; 38836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Op == 0) { 38936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "nop"; 39036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } else { 39136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned Stream = (SImm16 >> 8) & 0x3; 39236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Op == 1) 39336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "cut"; 39436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines else if (Op == 2) 39536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "emit"; 39636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines else if (Op == 3) 39736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "emit-cut"; 39836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << " stream " << Stream; 39936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } 40036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "), [m0] "; 40136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } else if (Msg == 1) 40236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "interrupt "; 40336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines else if (Msg == 15) 40436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "system "; 40536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines else 40636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines O << "unknown(" << Msg << ") "; 40736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines} 40836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 409cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeunevoid AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo, 410cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune raw_ostream &O) { 411cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs 412cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune // SIInsertWaits.cpp bits usage does not match ISA docs description but it 413cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune // works so it might be a misprint in docs. 414cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune unsigned SImm16 = MI->getOperand(OpNo).getImm(); 415cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune unsigned Vmcnt = SImm16 & 0xF; 416cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune unsigned Expcnt = (SImm16 >> 4) & 0xF; 417cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune unsigned Lgkmcnt = (SImm16 >> 8) & 0xF; 418cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune if (Vmcnt != 0xF) 419cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune O << "vmcnt(" << Vmcnt << ") "; 420cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune if (Expcnt != 0x7) 421cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune O << "expcnt(" << Expcnt << ") "; 422cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune if (Lgkmcnt != 0x7) 423cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune O << "lgkmcnt(" << Lgkmcnt << ")"; 424cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune} 425cf1f4c7dd19458f47a9ba720d90eec507d66c94aVincent Lejeune 426f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUGenAsmWriter.inc" 427