AMDGPUAsmBackend.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
11#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12#include "llvm/ADT/StringRef.h"
13#include "llvm/MC/MCAsmBackend.h"
14#include "llvm/MC/MCAssembler.h"
15#include "llvm/MC/MCObjectWriter.h"
16#include "llvm/MC/MCValue.h"
17#include "llvm/Support/TargetRegistry.h"
18
19using namespace llvm;
20
21namespace {
22
23class AMDGPUMCObjectWriter : public MCObjectWriter {
24public:
25  AMDGPUMCObjectWriter(raw_ostream &OS) : MCObjectWriter(OS, true) { }
26  virtual void ExecutePostLayoutBinding(MCAssembler &Asm,
27                                        const MCAsmLayout &Layout) {
28    //XXX: Implement if necessary.
29  }
30  void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
31                        const MCFragment *Fragment, const MCFixup &Fixup,
32                        MCValue Target, bool &IsPCRel,
33                        uint64_t &FixedValue) override {
34    assert(!"Not implemented");
35  }
36
37  virtual void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout);
38
39};
40
41class AMDGPUAsmBackend : public MCAsmBackend {
42public:
43  AMDGPUAsmBackend(const Target &T)
44    : MCAsmBackend() {}
45
46  virtual unsigned getNumFixupKinds() const { return 0; };
47  virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
48                          uint64_t Value, bool IsPCRel) const;
49  virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
50                                    const MCRelaxableFragment *DF,
51                                    const MCAsmLayout &Layout) const {
52    return false;
53  }
54  virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
55    assert(!"Not implemented");
56  }
57  virtual bool mayNeedRelaxation(const MCInst &Inst) const { return false; }
58  virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
59    return true;
60  }
61};
62
63} //End anonymous namespace
64
65void AMDGPUMCObjectWriter::WriteObject(MCAssembler &Asm,
66                                       const MCAsmLayout &Layout) {
67  for (MCAssembler::iterator I = Asm.begin(), E = Asm.end(); I != E; ++I) {
68    Asm.writeSectionData(I, Layout);
69  }
70}
71
72void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
73                                  unsigned DataSize, uint64_t Value,
74                                  bool IsPCRel) const {
75
76  uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
77  assert(Fixup.getKind() == FK_PCRel_4);
78  *Dst = (Value - 4) / 4;
79}
80
81//===----------------------------------------------------------------------===//
82// ELFAMDGPUAsmBackend class
83//===----------------------------------------------------------------------===//
84
85namespace {
86
87class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
88public:
89  ELFAMDGPUAsmBackend(const Target &T) : AMDGPUAsmBackend(T) { }
90
91  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
92    return createAMDGPUELFObjectWriter(OS);
93  }
94};
95
96} // end anonymous namespace
97
98MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
99                                           const MCRegisterInfo &MRI,
100                                           StringRef TT,
101                                           StringRef CPU) {
102  return new ELFAMDGPUAsmBackend(T);
103}
104