1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===// 2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// The LLVM Compiler Infrastructure 4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source 6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details. 7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \file 11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \brief This file provides AMDGPU specific target descriptions. 12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 13f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 14f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 15f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUMCTargetDesc.h" 16f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUMCAsmInfo.h" 17f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "InstPrinter/AMDGPUInstPrinter.h" 18f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/MC/MCCodeGenInfo.h" 19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/MC/MCInstrInfo.h" 20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/MC/MCRegisterInfo.h" 21f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/MC/MCStreamer.h" 22f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/MC/MCSubtargetInfo.h" 2358a2cbef4aac9ee7d530dfb690c78d6fc11a2371Chandler Carruth#include "llvm/MC/MachineLocation.h" 24f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/Support/ErrorHandling.h" 25f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/Support/TargetRegistry.h" 26f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 27dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesusing namespace llvm; 28dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 29f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#define GET_INSTRINFO_MC_DESC 30f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUGenInstrInfo.inc" 31f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 32f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#define GET_SUBTARGETINFO_MC_DESC 33f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUGenSubtargetInfo.inc" 34f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 35f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#define GET_REGINFO_MC_DESC 36f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUGenRegisterInfo.inc" 37f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 38f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardstatic MCInstrInfo *createAMDGPUMCInstrInfo() { 39f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MCInstrInfo *X = new MCInstrInfo(); 40f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard InitAMDGPUMCInstrInfo(X); 41f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return X; 42f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 43f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 44f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardstatic MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) { 45f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MCRegisterInfo *X = new MCRegisterInfo(); 46f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard InitAMDGPUMCRegisterInfo(X, 0); 47f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return X; 48f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 49f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 50f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardstatic MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, 51f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard StringRef FS) { 52f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MCSubtargetInfo * X = new MCSubtargetInfo(); 53f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS); 54f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return X; 55f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 56f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 57f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardstatic MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, 58f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard CodeModel::Model CM, 59f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard CodeGenOpt::Level OL) { 60f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MCCodeGenInfo *X = new MCCodeGenInfo(); 61f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard X->InitMCCodeGenInfo(RM, CM, OL); 62f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return X; 63f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 64f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 65f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardstatic MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T, 66f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned SyntaxVariant, 67f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MCAsmInfo &MAI, 68f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MCInstrInfo &MII, 69f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MCRegisterInfo &MRI, 70f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MCSubtargetInfo &STI) { 71f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return new AMDGPUInstPrinter(MAI, MII, MRI); 72f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 73f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 74f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardstatic MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, 75f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MCRegisterInfo &MRI, 76f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MCSubtargetInfo &STI, 77f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MCContext &Ctx) { 78f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { 79f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); 80f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } else { 8134f533a6c351d8b255810c9b4b8713700e66ee88Tom Stellard return createR600MCCodeEmitter(MCII, MRI, STI); 82f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 83f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 84f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 85f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardstatic MCStreamer *createMCStreamer(const Target &T, StringRef TT, 86f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MCContext &Ctx, MCAsmBackend &MAB, 87f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard raw_ostream &_OS, 88f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MCCodeEmitter *_Emitter, 8936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const MCSubtargetInfo &STI, 90f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool RelaxAll, 91f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool NoExecStack) { 9236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return createELFStreamer(Ctx, MAB, _OS, _Emitter, false, false); 93f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 94f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 95f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardextern "C" void LLVMInitializeR600TargetMC() { 96f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 97f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget); 98f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 99f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo); 100f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 101f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo); 102f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 103f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo); 104f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 105f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo); 106f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 107f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter); 108f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 109f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter); 110f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 111f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend); 112f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 113f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer); 114f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 115