AMDGPUMCTargetDesc.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief This file provides AMDGPU specific target descriptions.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPUMCTargetDesc.h"
16#include "AMDGPUMCAsmInfo.h"
17#include "InstPrinter/AMDGPUInstPrinter.h"
18#include "llvm/MC/MCCodeGenInfo.h"
19#include "llvm/MC/MCInstrInfo.h"
20#include "llvm/MC/MCRegisterInfo.h"
21#include "llvm/MC/MCStreamer.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/MachineLocation.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/TargetRegistry.h"
26
27using namespace llvm;
28
29#define GET_INSTRINFO_MC_DESC
30#include "AMDGPUGenInstrInfo.inc"
31
32#define GET_SUBTARGETINFO_MC_DESC
33#include "AMDGPUGenSubtargetInfo.inc"
34
35#define GET_REGINFO_MC_DESC
36#include "AMDGPUGenRegisterInfo.inc"
37
38static MCInstrInfo *createAMDGPUMCInstrInfo() {
39  MCInstrInfo *X = new MCInstrInfo();
40  InitAMDGPUMCInstrInfo(X);
41  return X;
42}
43
44static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
45  MCRegisterInfo *X = new MCRegisterInfo();
46  InitAMDGPUMCRegisterInfo(X, 0);
47  return X;
48}
49
50static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
51                                                   StringRef FS) {
52  MCSubtargetInfo * X = new MCSubtargetInfo();
53  InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
54  return X;
55}
56
57static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
58                                               CodeModel::Model CM,
59                                               CodeGenOpt::Level OL) {
60  MCCodeGenInfo *X = new MCCodeGenInfo();
61  X->InitMCCodeGenInfo(RM, CM, OL);
62  return X;
63}
64
65static MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T,
66                                                unsigned SyntaxVariant,
67                                                const MCAsmInfo &MAI,
68                                                const MCInstrInfo &MII,
69                                                const MCRegisterInfo &MRI,
70                                                const MCSubtargetInfo &STI) {
71  return new AMDGPUInstPrinter(MAI, MII, MRI);
72}
73
74static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
75                                                const MCRegisterInfo &MRI,
76                                                const MCSubtargetInfo &STI,
77                                                MCContext &Ctx) {
78  if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
79    return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
80  } else {
81    return createR600MCCodeEmitter(MCII, MRI, STI);
82  }
83}
84
85static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
86                                    MCContext &Ctx, MCAsmBackend &MAB,
87                                    raw_ostream &_OS,
88                                    MCCodeEmitter *_Emitter,
89                                    const MCSubtargetInfo &STI,
90                                    bool RelaxAll,
91                                    bool NoExecStack) {
92  return createELFStreamer(Ctx, MAB, _OS, _Emitter, false, false);
93}
94
95extern "C" void LLVMInitializeR600TargetMC() {
96
97  RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget);
98
99  TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo);
100
101  TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo);
102
103  TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo);
104
105  TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo);
106
107  TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter);
108
109  TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter);
110
111  TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend);
112
113  TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer);
114}
115