R600InstrInfo.h revision ac779b8494ad3d2f2ea40cb566552c0fb1b17363
19bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===// 29bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)// 39bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)// The LLVM Compiler Infrastructure 49bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)// 59bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 69bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)// License. See LICENSE.TXT for details. 79bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)// 89bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)//===----------------------------------------------------------------------===// 99bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)// 109bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)/// \file 119bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)/// \brief Interface definition for R600InstrInfo 129bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)// 139bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)//===----------------------------------------------------------------------===// 149bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 159bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)#ifndef R600INSTRUCTIONINFO_H_ 169bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)#define R600INSTRUCTIONINFO_H_ 179bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 189bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)#include "AMDGPUInstrInfo.h" 199bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)#include "R600Defines.h" 209bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)#include "R600RegisterInfo.h" 219bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)#include <map> 229bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 239bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles)namespace llvm { 249bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 259bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) class AMDGPUTargetMachine; 269bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) class DFAPacketizer; 279bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) class ScheduleDAG; 289bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) class MachineFunction; 299bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) class MachineInstr; 309bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) class MachineInstrBuilder; 3109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 329bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) class R600InstrInfo : public AMDGPUInstrInfo { 33bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) private: 34bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) const R600RegisterInfo RI; 35bfe3590b1806e3ff18f46ee3af5d4b83078f305aTorne (Richard Coles) const AMDGPUSubtarget &ST; 369bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 379bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) int getBranchInstr(const MachineOperand &op) const; 38f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) std::vector<std::pair<int, unsigned> > 399bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const; 409bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 419bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) public: 429bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) enum BankSwizzle { 439bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) ALU_VEC_012_SCL_210 = 0, 449bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) ALU_VEC_021_SCL_122, 459bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) ALU_VEC_120_SCL_212, 469bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) ALU_VEC_102_SCL_221, 479bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) ALU_VEC_201, 489bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) ALU_VEC_210 499bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) }; 509bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 519bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) explicit R600InstrInfo(AMDGPUTargetMachine &tm); 529bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 539bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) const R600RegisterInfo &getRegisterInfo() const; 549bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) virtual void copyPhysReg(MachineBasicBlock &MBB, 5506f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles) MachineBasicBlock::iterator MI, DebugLoc DL, 56d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) unsigned DestReg, unsigned SrcReg, 57d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool KillSrc) const; 589bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 599bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool isTrig(const MachineInstr &MI) const; 609bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool isPlaceHolderOpcode(unsigned opcode) const; 619bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool isReductionOp(unsigned opcode) const; 629bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool isCubeOp(unsigned opcode) const; 639bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 649bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// \returns true if this \p Opcode represents an ALU instruction. 65f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) bool isALUInstr(unsigned Opcode) const; 669bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool hasInstrModifiers(unsigned Opcode) const; 679bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool isLDSInstr(unsigned Opcode) const; 689bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 69d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isTransOnly(unsigned Opcode) const; 70d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isTransOnly(const MachineInstr *MI) const; 71d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isVectorOnly(unsigned Opcode) const; 72d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isVectorOnly(const MachineInstr *MI) const; 739bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool isExport(unsigned Opcode) const; 749bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 75d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool usesVertexCache(unsigned Opcode) const; 76d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool usesVertexCache(const MachineInstr *MI) const; 77d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool usesTextureCache(unsigned Opcode) const; 78d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool usesTextureCache(const MachineInstr *MI) const; 79d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 80d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool mustBeLastInClause(unsigned Opcode) const; 81d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool readsLDSSrcReg(const MachineInstr *MI) const; 829bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 839bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// \returns The operand index for the given source number. Legal values 849bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// for SrcNum are 0, 1, and 2. 859bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) int getSrcIdx(unsigned Opcode, unsigned SrcNum) const; 86d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// \returns The operand Index for the Sel operand given an index to one 87d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// of the instruction's src operands. 88d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) int getSelIdx(unsigned Opcode, unsigned SrcIdx) const; 89d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 90d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// \returns a pair for each src of an ALU instructions. 91d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// The first member of a pair is the register id. 92d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// If register is ALU_CONST, second member is SEL. 939bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// If register is ALU_LITERAL, second member is IMM. 949bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// Otherwise, second member value is undefined. 959bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) SmallVector<std::pair<MachineOperand *, int64_t>, 3> 969bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) getSrcs(MachineInstr *MI) const; 979bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 989bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) unsigned isLegalUpTo( 999bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, 1009bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) const std::vector<R600InstrInfo::BankSwizzle> &Swz, 1019bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) const std::vector<std::pair<int, unsigned> > &TransSrcs, 1029bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) R600InstrInfo::BankSwizzle TransSwz) const; 1039bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 1049bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool FindSwizzleForVectorSlot( 1059bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, 1069bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, 1079bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) const std::vector<std::pair<int, unsigned> > &TransSrcs, 1089bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) R600InstrInfo::BankSwizzle TransSwz) const; 1099bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 1109bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 1119bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// returns true and the first (in lexical order) BankSwizzle affectation 1129bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// starting from the one already provided in the Instruction Group MIs that 1139bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// fits Read Port limitations in BS if available. Otherwise returns false 1149bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// and undefined content in BS. 1159bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// isLastAluTrans should be set if the last Alu of MIs will be executed on 1169bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to 1179bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// apply to the last instruction. 1189bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) /// PV holds GPR to PV registers in the Instruction Group MIs. 1199bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs, 1209bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) const DenseMap<unsigned, unsigned> &PV, 121d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) std::vector<BankSwizzle> &BS, 122d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isLastAluTrans) const; 123d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 124d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// An instruction group can only access 2 channel pair (either [XY] or [ZW]) 125d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// from KCache bank on R700+. This function check if MI set in input meet 126d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// this limitations 127d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const; 128d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// Same but using const index set instead of MI set. 129d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool fitsConstReadLimitations(const std::vector<unsigned>&) const; 130d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 131d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// \breif Vector instructions are instructions that must fill all 132d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// instruction slots within an instruction group. 133d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isVector(const MachineInstr &MI) const; 134d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 135d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, 136d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) int64_t Imm) const; 137d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 138d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) virtual unsigned getIEQOpcode() const; 139d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) virtual bool isMov(unsigned Opcode) const; 140d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 141d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM, 142d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) const ScheduleDAG *DAG) const; 143d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 144d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 145d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 146d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 147d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const; 148d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 149d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const; 150d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 151d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) unsigned RemoveBranch(MachineBasicBlock &MBB) const; 152d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 153d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isPredicated(const MachineInstr *MI) const; 154d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 155d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isPredicable(MachineInstr *MI) const; 156d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 157d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool 158d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 159d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) const BranchProbability &Probability) const; 160d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 161d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 162d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) unsigned ExtraPredCycles, 163d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) const BranchProbability &Probability) const ; 164d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 165d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool 166d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) isProfitableToIfCvt(MachineBasicBlock &TMBB, 167d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) unsigned NumTCycles, unsigned ExtraTCycles, 168d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) MachineBasicBlock &FMBB, 169d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) unsigned NumFCycles, unsigned ExtraFCycles, 170d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) const BranchProbability &Probability) const; 171d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 172d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool DefinesPredicate(MachineInstr *MI, 173d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) std::vector<MachineOperand> &Pred) const; 174d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 175d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 176d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) const SmallVectorImpl<MachineOperand> &Pred2) const; 177d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 178d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 179d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) MachineBasicBlock &FMBB) const; 1809bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 1819bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) bool PredicateInstruction(MachineInstr *MI, 1829bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) const SmallVectorImpl<MachineOperand> &Pred) const; 1839bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 1849bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) unsigned int getInstrLatency(const InstrItineraryData *ItinData, 1859bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) const MachineInstr *MI, 1869bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) unsigned *PredCost = 0) const; 1879bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 1889bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) virtual int getInstrLatency(const InstrItineraryData *ItinData, 189d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) SDNode *Node) const { return 1;} 190d6cdb82654e8f3343a693ca752d5c4cee0324e17Torne (Richard Coles) 191d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// \returns a list of all the registers that may be accesed using indirect 192d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) /// addressing. 193d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const; 1949bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 19506f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles) virtual int getIndirectIndexBegin(const MachineFunction &MF) const; 1969bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 1979bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) virtual int getIndirectIndexEnd(const MachineFunction &MF) const; 1989bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 199d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 2009bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) virtual unsigned calculateIndirectAddress(unsigned RegIndex, 2011e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) unsigned Channel) const; 20207a852d8c1953036774d8f3b65d18dcfea3bb4a2Ben Murdoch 2039bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) virtual const TargetRegisterClass *getIndirectAddrStoreRegClass( 2049bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) unsigned SourceReg) const; 205d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 2069bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const; 2079bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 2089bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 2099bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) MachineBasicBlock::iterator I, 2109bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) unsigned ValueReg, unsigned Address, 2119bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) unsigned OffsetReg) const; 2129bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) 2139bbd2f5e390b01907d97ecffde80aa1b06113aacTorne (Richard Coles) virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 214 MachineBasicBlock::iterator I, 215 unsigned ValueReg, unsigned Address, 216 unsigned OffsetReg) const; 217 218 virtual const TargetRegisterClass *getSuperIndirectRegClass() const; 219 220 unsigned getMaxAlusPerClause() const; 221 222 ///buildDefaultInstruction - This function returns a MachineInstr with 223 /// all the instruction modifiers initialized to their default values. 224 /// You can use this function to avoid manually specifying each instruction 225 /// modifier operand when building a new instruction. 226 /// 227 /// \returns a MachineInstr with all the instruction modifiers initialized 228 /// to their default values. 229 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, 230 MachineBasicBlock::iterator I, 231 unsigned Opcode, 232 unsigned DstReg, 233 unsigned Src0Reg, 234 unsigned Src1Reg = 0) const; 235 236 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB, 237 MachineInstr *MI, 238 unsigned Slot, 239 unsigned DstReg) const; 240 241 MachineInstr *buildMovImm(MachineBasicBlock &BB, 242 MachineBasicBlock::iterator I, 243 unsigned DstReg, 244 uint64_t Imm) const; 245 246 /// \brief Get the index of Op in the MachineInstr. 247 /// 248 /// \returns -1 if the Instruction does not contain the specified \p Op. 249 int getOperandIdx(const MachineInstr &MI, unsigned Op) const; 250 251 /// \brief Get the index of \p Op for the given Opcode. 252 /// 253 /// \returns -1 if the Instruction does not contain the specified \p Op. 254 int getOperandIdx(unsigned Opcode, unsigned Op) const; 255 256 /// \brief Helper function for setting instruction flag values. 257 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const; 258 259 /// \returns true if this instruction has an operand for storing target flags. 260 bool hasFlagOperand(const MachineInstr &MI) const; 261 262 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand. 263 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 264 265 ///\brief Determine if the specified \p Flag is set on this \p Operand. 266 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const; 267 268 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2) 269 /// \param Flag The flag being set. 270 /// 271 /// \returns the operand containing the flags for this instruction. 272 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0, 273 unsigned Flag = 0) const; 274 275 /// \brief Clear the specified flag on the instruction. 276 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 277}; 278 279namespace AMDGPU { 280 281int getLDSNoRetOp(uint16_t Opcode); 282 283} //End namespace AMDGPU 284 285} // End llvm namespace 286 287#endif // R600INSTRINFO_H_ 288