R600InstrInfo.h revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb
1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===// 2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// The LLVM Compiler Infrastructure 4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source 6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details. 7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \file 11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \brief Interface definition for R600InstrInfo 12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 13f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 14f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 15f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#ifndef R600INSTRUCTIONINFO_H_ 16f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#define R600INSTRUCTIONINFO_H_ 17f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 18f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUInstrInfo.h" 19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "R600Defines.h" 20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "R600RegisterInfo.h" 21f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include <map> 22f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 23f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardnamespace llvm { 24f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 25f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard class AMDGPUTargetMachine; 26f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard class DFAPacketizer; 27f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard class ScheduleDAG; 28f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard class MachineFunction; 29f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard class MachineInstr; 30f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard class MachineInstrBuilder; 31f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 32f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard class R600InstrInfo : public AMDGPUInstrInfo { 33f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard private: 34f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const R600RegisterInfo RI; 35f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 3625c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune std::vector<std::pair<int, unsigned> > 377d1a0d4e3ebf058a8b1d0dea9b6119444ed041c8Vincent Lejeune ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const; 38f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 39cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 40cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 41cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MachineBasicBlock::iterator I, 42cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines unsigned ValueReg, unsigned Address, 43cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines unsigned OffsetReg, 44cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines unsigned AddrChan) const; 45cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 46cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 47cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MachineBasicBlock::iterator I, 48cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines unsigned ValueReg, unsigned Address, 49cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines unsigned OffsetReg, 50cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines unsigned AddrChan) const; 51f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard public: 5225c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune enum BankSwizzle { 537d1a0d4e3ebf058a8b1d0dea9b6119444ed041c8Vincent Lejeune ALU_VEC_012_SCL_210 = 0, 547d1a0d4e3ebf058a8b1d0dea9b6119444ed041c8Vincent Lejeune ALU_VEC_021_SCL_122, 557d1a0d4e3ebf058a8b1d0dea9b6119444ed041c8Vincent Lejeune ALU_VEC_120_SCL_212, 567d1a0d4e3ebf058a8b1d0dea9b6119444ed041c8Vincent Lejeune ALU_VEC_102_SCL_221, 5725c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune ALU_VEC_201, 5825c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune ALU_VEC_210 5925c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune }; 6025c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune 61cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines explicit R600InstrInfo(const AMDGPUSubtarget &st); 62f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 63dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const R600RegisterInfo &getRegisterInfo() const override; 64dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines void copyPhysReg(MachineBasicBlock &MBB, 65dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock::iterator MI, DebugLoc DL, 66dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned DestReg, unsigned SrcReg, 67dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool KillSrc) const override; 689e78ba4ddcf80e2e292220b4a07a9baba21cfa15Bill Wendling bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 69dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock::iterator MBBI) const override; 70f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 71f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool isTrig(const MachineInstr &MI) const; 72f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool isPlaceHolderOpcode(unsigned opcode) const; 73f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool isReductionOp(unsigned opcode) const; 74f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool isCubeOp(unsigned opcode) const; 75f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 76f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \returns true if this \p Opcode represents an ALU instruction. 77f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool isALUInstr(unsigned Opcode) const; 78e3d4cbc7d25061441adafa47450a31571c87bf85Tom Stellard bool hasInstrModifiers(unsigned Opcode) const; 79e3d4cbc7d25061441adafa47450a31571c87bf85Tom Stellard bool isLDSInstr(unsigned Opcode) const; 8019a99df130f5747da950faf4ca5170d71f05594cTom Stellard bool isLDSNoRetInstr(unsigned Opcode) const; 8119a99df130f5747da950faf4ca5170d71f05594cTom Stellard bool isLDSRetInstr(unsigned Opcode) const; 82f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 83dfef7cbfc6a96d129b99750f554c7dbc000d3228Vincent Lejeune /// \returns true if this \p Opcode represents an ALU instruction or an 84dfef7cbfc6a96d129b99750f554c7dbc000d3228Vincent Lejeune /// instruction that will be lowered in ExpandSpecialInstrs Pass. 85dfef7cbfc6a96d129b99750f554c7dbc000d3228Vincent Lejeune bool canBeConsideredALU(const MachineInstr *MI) const; 86dfef7cbfc6a96d129b99750f554c7dbc000d3228Vincent Lejeune 87abcde265b1f8f8d29a4542bfd87ee6f8fb1537a0Vincent Lejeune bool isTransOnly(unsigned Opcode) const; 88abcde265b1f8f8d29a4542bfd87ee6f8fb1537a0Vincent Lejeune bool isTransOnly(const MachineInstr *MI) const; 89b3df27d4402d8c8fc81d5acec812035360806cdcVincent Lejeune bool isVectorOnly(unsigned Opcode) const; 90b3df27d4402d8c8fc81d5acec812035360806cdcVincent Lejeune bool isVectorOnly(const MachineInstr *MI) const; 91e7ac2ed1c268891a856ab38db1e34372a79da86aTom Stellard bool isExport(unsigned Opcode) const; 92abcde265b1f8f8d29a4542bfd87ee6f8fb1537a0Vincent Lejeune 93631591e6f3e5119d8a8b1c853279bc4ac7ace4a0Vincent Lejeune bool usesVertexCache(unsigned Opcode) const; 94631591e6f3e5119d8a8b1c853279bc4ac7ace4a0Vincent Lejeune bool usesVertexCache(const MachineInstr *MI) const; 95631591e6f3e5119d8a8b1c853279bc4ac7ace4a0Vincent Lejeune bool usesTextureCache(unsigned Opcode) const; 96631591e6f3e5119d8a8b1c853279bc4ac7ace4a0Vincent Lejeune bool usesTextureCache(const MachineInstr *MI) const; 97631591e6f3e5119d8a8b1c853279bc4ac7ace4a0Vincent Lejeune 98cedcfee405a22b245e869abe8609f094df34085aTom Stellard bool mustBeLastInClause(unsigned Opcode) const; 9904c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard bool usesAddressRegister(MachineInstr *MI) const; 10004c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard bool definesAddressRegister(MachineInstr *MI) const; 101ac779b8494ad3d2f2ea40cb566552c0fb1b17363Tom Stellard bool readsLDSSrcReg(const MachineInstr *MI) const; 102cedcfee405a22b245e869abe8609f094df34085aTom Stellard 10358d3335cb9d2a40bd15c29a12ba045163295190eTom Stellard /// \returns The operand index for the given source number. Legal values 10458d3335cb9d2a40bd15c29a12ba045163295190eTom Stellard /// for SrcNum are 0, 1, and 2. 10558d3335cb9d2a40bd15c29a12ba045163295190eTom Stellard int getSrcIdx(unsigned Opcode, unsigned SrcNum) const; 10658d3335cb9d2a40bd15c29a12ba045163295190eTom Stellard /// \returns The operand Index for the Sel operand given an index to one 10758d3335cb9d2a40bd15c29a12ba045163295190eTom Stellard /// of the instruction's src operands. 10858d3335cb9d2a40bd15c29a12ba045163295190eTom Stellard int getSelIdx(unsigned Opcode, unsigned SrcIdx) const; 10958d3335cb9d2a40bd15c29a12ba045163295190eTom Stellard 11025c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// \returns a pair for each src of an ALU instructions. 11125c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// The first member of a pair is the register id. 11225c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// If register is ALU_CONST, second member is SEL. 11325c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// If register is ALU_LITERAL, second member is IMM. 11425c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// Otherwise, second member value is undefined. 11525c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune SmallVector<std::pair<MachineOperand *, int64_t>, 3> 11625c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune getSrcs(MachineInstr *MI) const; 11725c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune 1188f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune unsigned isLegalUpTo( 1198f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, 1208f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune const std::vector<R600InstrInfo::BankSwizzle> &Swz, 1218f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune const std::vector<std::pair<int, unsigned> > &TransSrcs, 1228f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune R600InstrInfo::BankSwizzle TransSwz) const; 1238f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune 1248f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune bool FindSwizzleForVectorSlot( 1258f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, 1268f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, 1278f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune const std::vector<std::pair<int, unsigned> > &TransSrcs, 1288f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune R600InstrInfo::BankSwizzle TransSwz) const; 129e3d4cbc7d25061441adafa47450a31571c87bf85Tom Stellard 13025c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 13125c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// returns true and the first (in lexical order) BankSwizzle affectation 13225c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// starting from the one already provided in the Instruction Group MIs that 13325c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// fits Read Port limitations in BS if available. Otherwise returns false 13425c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// and undefined content in BS. 1358f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune /// isLastAluTrans should be set if the last Alu of MIs will be executed on 1368f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to 1378f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune /// apply to the last instruction. 13825c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune /// PV holds GPR to PV registers in the Instruction Group MIs. 13925c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs, 14025c209e9a262b623deca60fb6b886907e22c941bVincent Lejeune const DenseMap<unsigned, unsigned> &PV, 1418f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune std::vector<BankSwizzle> &BS, 1428f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune bool isLastAluTrans) const; 1438f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune 1448f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune /// An instruction group can only access 2 channel pair (either [XY] or [ZW]) 1458f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune /// from KCache bank on R700+. This function check if MI set in input meet 1468f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune /// this limitations 1478f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const; 1488f9fbd67c3f803f7397843fdf4b2a7b7ca10189eVincent Lejeune /// Same but using const index set instead of MI set. 1493ab0ba3cd8a499ebcc7eda3d7585c5ab4e7f0711Vincent Lejeune bool fitsConstReadLimitations(const std::vector<unsigned>&) const; 1503ab0ba3cd8a499ebcc7eda3d7585c5ab4e7f0711Vincent Lejeune 15136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// \brief Vector instructions are instructions that must fill all 152f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// instruction slots within an instruction group. 153f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool isVector(const MachineInstr &MI) const; 154f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 155dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned getIEQOpcode() const override; 156dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool isMov(unsigned Opcode) const override; 157f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 158f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM, 159dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const ScheduleDAG *DAG) const override; 160f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 161dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 162f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 163f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 164dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; 165f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 166dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override; 167f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 168dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 169f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 170dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool isPredicated(const MachineInstr *MI) const override; 171f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 172dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool isPredicable(MachineInstr *MI) const override; 173f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 174f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool 175f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 176dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const BranchProbability &Probability) const override; 177f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 178f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 179f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned ExtraPredCycles, 180dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const BranchProbability &Probability) const override ; 181f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 182f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool 183f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard isProfitableToIfCvt(MachineBasicBlock &TMBB, 184f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned NumTCycles, unsigned ExtraTCycles, 185f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock &FMBB, 186f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned NumFCycles, unsigned ExtraFCycles, 187dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const BranchProbability &Probability) const override; 188f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 189f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool DefinesPredicate(MachineInstr *MI, 190dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines std::vector<MachineOperand> &Pred) const override; 191f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 192f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 193dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const SmallVectorImpl<MachineOperand> &Pred2) const override; 194f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 195f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 196dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock &FMBB) const override; 197f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 198f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool PredicateInstruction(MachineInstr *MI, 199dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const SmallVectorImpl<MachineOperand> &Pred) const override; 200f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 201dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned int getPredicationCost(const MachineInstr *) const override; 202d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 203f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned int getInstrLatency(const InstrItineraryData *ItinData, 204f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const MachineInstr *MI, 205dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned *PredCost = nullptr) const override; 206f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 207dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int getInstrLatency(const InstrItineraryData *ItinData, 208dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines SDNode *Node) const override { return 1;} 209f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 210cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 211cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 212a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard /// \brief Reserve the registers that may be accesed using indirect addressing. 213a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard void reserveIndirectRegisters(BitVector &Reserved, 214a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard const MachineFunction &MF) const; 215c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 216dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned calculateIndirectAddress(unsigned RegIndex, 217dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned Channel) const override; 218c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 219dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *getIndirectAddrRegClass() const override; 220c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 221dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 222dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock::iterator I, 223dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned ValueReg, unsigned Address, 224dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned OffsetReg) const override; 225c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 226dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 227dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock::iterator I, 228dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned ValueReg, unsigned Address, 229dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned OffsetReg) const override; 230c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 231dae2a20a56b28b4685249982a80a0043b7673e09Vincent Lejeune unsigned getMaxAlusPerClause() const; 232c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard 233c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard ///buildDefaultInstruction - This function returns a MachineInstr with 234c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8Tom Stellard /// all the instruction modifiers initialized to their default values. 235f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// You can use this function to avoid manually specifying each instruction 236f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// modifier operand when building a new instruction. 237f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// 238f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \returns a MachineInstr with all the instruction modifiers initialized 239f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// to their default values. 240f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, 241f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator I, 242f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned Opcode, 243f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned DstReg, 244f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned Src0Reg, 245f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned Src1Reg = 0) const; 246f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 2474ed9917147b1d1f2616f7c941bbe6999b979f510Vincent Lejeune MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB, 2484ed9917147b1d1f2616f7c941bbe6999b979f510Vincent Lejeune MachineInstr *MI, 2494ed9917147b1d1f2616f7c941bbe6999b979f510Vincent Lejeune unsigned Slot, 2504ed9917147b1d1f2616f7c941bbe6999b979f510Vincent Lejeune unsigned DstReg) const; 2514ed9917147b1d1f2616f7c941bbe6999b979f510Vincent Lejeune 252f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineInstr *buildMovImm(MachineBasicBlock &BB, 253f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineBasicBlock::iterator I, 254f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned DstReg, 255f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard uint64_t Imm) const; 256f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 25704c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard MachineInstr *buildMovInstr(MachineBasicBlock *MBB, 25804c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard MachineBasicBlock::iterator I, 259dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned DstReg, unsigned SrcReg) const override; 26004c559569f87d755c3f2828a765f5eb7308e6753Tom Stellard 261f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \brief Get the index of Op in the MachineInstr. 262f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// 263f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \returns -1 if the Instruction does not contain the specified \p Op. 2645e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0Tom Stellard int getOperandIdx(const MachineInstr &MI, unsigned Op) const; 265f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 266f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \brief Get the index of \p Op for the given Opcode. 267f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// 268f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \returns -1 if the Instruction does not contain the specified \p Op. 2695e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0Tom Stellard int getOperandIdx(unsigned Opcode, unsigned Op) const; 270f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 271f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \brief Helper function for setting instruction flag values. 2725e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0Tom Stellard void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const; 273f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 274f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \returns true if this instruction has an operand for storing target flags. 275f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool hasFlagOperand(const MachineInstr &MI) const; 276f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 277f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard ///\brief Add one of the MO_FLAG* flags to the specified \p Operand. 278f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 279f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 280f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard ///\brief Determine if the specified \p Flag is set on this \p Operand. 281f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const; 282f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 283f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2) 284f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \param Flag The flag being set. 285f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// 286f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \returns the operand containing the flags for this instruction. 287f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0, 288f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard unsigned Flag = 0) const; 289f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 290f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard /// \brief Clear the specified flag on the instruction. 291f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 292f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard}; 293f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 29479916948e1fd176a3898b596b679cc9dba3d40a8Tom Stellardnamespace AMDGPU { 29579916948e1fd176a3898b596b679cc9dba3d40a8Tom Stellard 29679916948e1fd176a3898b596b679cc9dba3d40a8Tom Stellardint getLDSNoRetOp(uint16_t Opcode); 29779916948e1fd176a3898b596b679cc9dba3d40a8Tom Stellard 29879916948e1fd176a3898b596b679cc9dba3d40a8Tom Stellard} //End namespace AMDGPU 29979916948e1fd176a3898b596b679cc9dba3d40a8Tom Stellard 300f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} // End llvm namespace 301f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 302f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#endif // R600INSTRINFO_H_ 303