R600InstrInfo.h revision 19a99df130f5747da950faf4ca5170d71f05594c 
1//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600InstrInfo
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef R600INSTRUCTIONINFO_H_
16#define R600INSTRUCTIONINFO_H_
17
18#include "AMDGPUInstrInfo.h"
19#include "R600Defines.h"
20#include "R600RegisterInfo.h"
21#include <map>
22
23namespace llvm {
24
25  class AMDGPUTargetMachine;
26  class DFAPacketizer;
27  class ScheduleDAG;
28  class MachineFunction;
29  class MachineInstr;
30  class MachineInstrBuilder;
31
32  class R600InstrInfo : public AMDGPUInstrInfo {
33  private:
34  const R600RegisterInfo RI;
35  const AMDGPUSubtarget &ST;
36
37  int getBranchInstr(const MachineOperand &op) const;
38  std::vector<std::pair<int, unsigned> >
39  ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
40
41  public:
42  enum BankSwizzle {
43    ALU_VEC_012_SCL_210 = 0,
44    ALU_VEC_021_SCL_122,
45    ALU_VEC_120_SCL_212,
46    ALU_VEC_102_SCL_221,
47    ALU_VEC_201,
48    ALU_VEC_210
49  };
50
51  explicit R600InstrInfo(AMDGPUTargetMachine &tm);
52
53  const R600RegisterInfo &getRegisterInfo() const;
54  virtual void copyPhysReg(MachineBasicBlock &MBB,
55                           MachineBasicBlock::iterator MI, DebugLoc DL,
56                           unsigned DestReg, unsigned SrcReg,
57                           bool KillSrc) const;
58
59  bool isTrig(const MachineInstr &MI) const;
60  bool isPlaceHolderOpcode(unsigned opcode) const;
61  bool isReductionOp(unsigned opcode) const;
62  bool isCubeOp(unsigned opcode) const;
63
64  /// \returns true if this \p Opcode represents an ALU instruction.
65  bool isALUInstr(unsigned Opcode) const;
66  bool hasInstrModifiers(unsigned Opcode) const;
67  bool isLDSInstr(unsigned Opcode) const;
68  bool isLDSNoRetInstr(unsigned Opcode) const;
69  bool isLDSRetInstr(unsigned Opcode) const;
70
71  /// \returns true if this \p Opcode represents an ALU instruction or an
72  /// instruction that will be lowered in ExpandSpecialInstrs Pass.
73  bool canBeConsideredALU(const MachineInstr *MI) const;
74
75  bool isTransOnly(unsigned Opcode) const;
76  bool isTransOnly(const MachineInstr *MI) const;
77  bool isVectorOnly(unsigned Opcode) const;
78  bool isVectorOnly(const MachineInstr *MI) const;
79  bool isExport(unsigned Opcode) const;
80
81  bool usesVertexCache(unsigned Opcode) const;
82  bool usesVertexCache(const MachineInstr *MI) const;
83  bool usesTextureCache(unsigned Opcode) const;
84  bool usesTextureCache(const MachineInstr *MI) const;
85
86  bool mustBeLastInClause(unsigned Opcode) const;
87  bool usesAddressRegister(MachineInstr *MI) const;
88  bool definesAddressRegister(MachineInstr *MI) const;
89  bool readsLDSSrcReg(const MachineInstr *MI) const;
90
91  /// \returns The operand index for the given source number.  Legal values
92  /// for SrcNum are 0, 1, and 2.
93  int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
94  /// \returns The operand Index for the Sel operand given an index to one
95  /// of the instruction's src operands.
96  int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
97
98  /// \returns a pair for each src of an ALU instructions.
99  /// The first member of a pair is the register id.
100  /// If register is ALU_CONST, second member is SEL.
101  /// If register is ALU_LITERAL, second member is IMM.
102  /// Otherwise, second member value is undefined.
103  SmallVector<std::pair<MachineOperand *, int64_t>, 3>
104      getSrcs(MachineInstr *MI) const;
105
106  unsigned  isLegalUpTo(
107    const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
108    const std::vector<R600InstrInfo::BankSwizzle> &Swz,
109    const std::vector<std::pair<int, unsigned> > &TransSrcs,
110    R600InstrInfo::BankSwizzle TransSwz) const;
111
112  bool FindSwizzleForVectorSlot(
113    const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
114    std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
115    const std::vector<std::pair<int, unsigned> > &TransSrcs,
116    R600InstrInfo::BankSwizzle TransSwz) const;
117
118  /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
119  /// returns true and the first (in lexical order) BankSwizzle affectation
120  /// starting from the one already provided in the Instruction Group MIs that
121  /// fits Read Port limitations in BS if available. Otherwise returns false
122  /// and undefined content in BS.
123  /// isLastAluTrans should be set if the last Alu of MIs will be executed on
124  /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
125  /// apply to the last instruction.
126  /// PV holds GPR to PV registers in the Instruction Group MIs.
127  bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
128                               const DenseMap<unsigned, unsigned> &PV,
129                               std::vector<BankSwizzle> &BS,
130                               bool isLastAluTrans) const;
131
132  /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
133  /// from KCache bank on R700+. This function check if MI set in input meet
134  /// this limitations
135  bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
136  /// Same but using const index set instead of MI set.
137  bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
138
139  /// \breif Vector instructions are instructions that must fill all
140  /// instruction slots within an instruction group.
141  bool isVector(const MachineInstr &MI) const;
142
143  virtual unsigned getIEQOpcode() const;
144  virtual bool isMov(unsigned Opcode) const;
145
146  DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
147                                           const ScheduleDAG *DAG) const;
148
149  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
150
151  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
152                     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
153
154  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
155
156  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
157
158  bool isPredicated(const MachineInstr *MI) const;
159
160  bool isPredicable(MachineInstr *MI) const;
161
162  bool
163   isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
164                             const BranchProbability &Probability) const;
165
166  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
167                           unsigned ExtraPredCycles,
168                           const BranchProbability &Probability) const ;
169
170  bool
171   isProfitableToIfCvt(MachineBasicBlock &TMBB,
172                       unsigned NumTCycles, unsigned ExtraTCycles,
173                       MachineBasicBlock &FMBB,
174                       unsigned NumFCycles, unsigned ExtraFCycles,
175                       const BranchProbability &Probability) const;
176
177  bool DefinesPredicate(MachineInstr *MI,
178                                  std::vector<MachineOperand> &Pred) const;
179
180  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
181                         const SmallVectorImpl<MachineOperand> &Pred2) const;
182
183  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
184                                          MachineBasicBlock &FMBB) const;
185
186  bool PredicateInstruction(MachineInstr *MI,
187                        const SmallVectorImpl<MachineOperand> &Pred) const;
188
189  unsigned int getPredicationCost(const MachineInstr *) const;
190
191  unsigned int getInstrLatency(const InstrItineraryData *ItinData,
192                               const MachineInstr *MI,
193                               unsigned *PredCost = 0) const;
194
195  virtual int getInstrLatency(const InstrItineraryData *ItinData,
196                              SDNode *Node) const { return 1;}
197
198  /// \brief Reserve the registers that may be accesed using indirect addressing.
199  void reserveIndirectRegisters(BitVector &Reserved,
200                                const MachineFunction &MF) const;
201
202  virtual unsigned calculateIndirectAddress(unsigned RegIndex,
203                                            unsigned Channel) const;
204
205  virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
206
207  virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
208                                  MachineBasicBlock::iterator I,
209                                  unsigned ValueReg, unsigned Address,
210                                  unsigned OffsetReg) const;
211
212  virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
213                                  MachineBasicBlock::iterator I,
214                                  unsigned ValueReg, unsigned Address,
215                                  unsigned OffsetReg) const;
216
217  unsigned getMaxAlusPerClause() const;
218
219  ///buildDefaultInstruction - This function returns a MachineInstr with
220  /// all the instruction modifiers initialized to their default values.
221  /// You can use this function to avoid manually specifying each instruction
222  /// modifier operand when building a new instruction.
223  ///
224  /// \returns a MachineInstr with all the instruction modifiers initialized
225  /// to their default values.
226  MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
227                                              MachineBasicBlock::iterator I,
228                                              unsigned Opcode,
229                                              unsigned DstReg,
230                                              unsigned Src0Reg,
231                                              unsigned Src1Reg = 0) const;
232
233  MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
234                                             MachineInstr *MI,
235                                             unsigned Slot,
236                                             unsigned DstReg) const;
237
238  MachineInstr *buildMovImm(MachineBasicBlock &BB,
239                                  MachineBasicBlock::iterator I,
240                                  unsigned DstReg,
241                                  uint64_t Imm) const;
242
243  MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
244                              MachineBasicBlock::iterator I,
245                              unsigned DstReg, unsigned SrcReg) const;
246
247  /// \brief Get the index of Op in the MachineInstr.
248  ///
249  /// \returns -1 if the Instruction does not contain the specified \p Op.
250  int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
251
252  /// \brief Get the index of \p Op for the given Opcode.
253  ///
254  /// \returns -1 if the Instruction does not contain the specified \p Op.
255  int getOperandIdx(unsigned Opcode, unsigned Op) const;
256
257  /// \brief Helper function for setting instruction flag values.
258  void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
259
260  /// \returns true if this instruction has an operand for storing target flags.
261  bool hasFlagOperand(const MachineInstr &MI) const;
262
263  ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
264  void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
265
266  ///\brief Determine if the specified \p Flag is set on this \p Operand.
267  bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
268
269  /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
270  /// \param Flag The flag being set.
271  ///
272  /// \returns the operand containing the flags for this instruction.
273  MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
274                            unsigned Flag = 0) const;
275
276  /// \brief Clear the specified flag on the instruction.
277  void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
278};
279
280namespace AMDGPU {
281
282int getLDSNoRetOp(uint16_t Opcode);
283
284} //End namespace AMDGPU
285
286} // End llvm namespace
287
288#endif // R600INSTRINFO_H_
289