R600InstrInfo.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600InstrInfo
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef R600INSTRUCTIONINFO_H_
16#define R600INSTRUCTIONINFO_H_
17
18#include "AMDGPUInstrInfo.h"
19#include "R600Defines.h"
20#include "R600RegisterInfo.h"
21#include <map>
22
23namespace llvm {
24
25  class AMDGPUTargetMachine;
26  class DFAPacketizer;
27  class ScheduleDAG;
28  class MachineFunction;
29  class MachineInstr;
30  class MachineInstrBuilder;
31
32  class R600InstrInfo : public AMDGPUInstrInfo {
33  private:
34  const R600RegisterInfo RI;
35  const AMDGPUSubtarget &ST;
36
37  int getBranchInstr(const MachineOperand &op) const;
38  std::vector<std::pair<int, unsigned> >
39  ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
40
41  public:
42  enum BankSwizzle {
43    ALU_VEC_012_SCL_210 = 0,
44    ALU_VEC_021_SCL_122,
45    ALU_VEC_120_SCL_212,
46    ALU_VEC_102_SCL_221,
47    ALU_VEC_201,
48    ALU_VEC_210
49  };
50
51  explicit R600InstrInfo(AMDGPUTargetMachine &tm);
52
53  const R600RegisterInfo &getRegisterInfo() const;
54  virtual void copyPhysReg(MachineBasicBlock &MBB,
55                           MachineBasicBlock::iterator MI, DebugLoc DL,
56                           unsigned DestReg, unsigned SrcReg,
57                           bool KillSrc) const;
58  bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
59                           MachineBasicBlock::iterator MBBI) const;
60
61  bool isTrig(const MachineInstr &MI) const;
62  bool isPlaceHolderOpcode(unsigned opcode) const;
63  bool isReductionOp(unsigned opcode) const;
64  bool isCubeOp(unsigned opcode) const;
65
66  /// \returns true if this \p Opcode represents an ALU instruction.
67  bool isALUInstr(unsigned Opcode) const;
68  bool hasInstrModifiers(unsigned Opcode) const;
69  bool isLDSInstr(unsigned Opcode) const;
70  bool isLDSNoRetInstr(unsigned Opcode) const;
71  bool isLDSRetInstr(unsigned Opcode) const;
72
73  /// \returns true if this \p Opcode represents an ALU instruction or an
74  /// instruction that will be lowered in ExpandSpecialInstrs Pass.
75  bool canBeConsideredALU(const MachineInstr *MI) const;
76
77  bool isTransOnly(unsigned Opcode) const;
78  bool isTransOnly(const MachineInstr *MI) const;
79  bool isVectorOnly(unsigned Opcode) const;
80  bool isVectorOnly(const MachineInstr *MI) const;
81  bool isExport(unsigned Opcode) const;
82
83  bool usesVertexCache(unsigned Opcode) const;
84  bool usesVertexCache(const MachineInstr *MI) const;
85  bool usesTextureCache(unsigned Opcode) const;
86  bool usesTextureCache(const MachineInstr *MI) const;
87
88  bool mustBeLastInClause(unsigned Opcode) const;
89  bool usesAddressRegister(MachineInstr *MI) const;
90  bool definesAddressRegister(MachineInstr *MI) const;
91  bool readsLDSSrcReg(const MachineInstr *MI) const;
92
93  /// \returns The operand index for the given source number.  Legal values
94  /// for SrcNum are 0, 1, and 2.
95  int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
96  /// \returns The operand Index for the Sel operand given an index to one
97  /// of the instruction's src operands.
98  int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
99
100  /// \returns a pair for each src of an ALU instructions.
101  /// The first member of a pair is the register id.
102  /// If register is ALU_CONST, second member is SEL.
103  /// If register is ALU_LITERAL, second member is IMM.
104  /// Otherwise, second member value is undefined.
105  SmallVector<std::pair<MachineOperand *, int64_t>, 3>
106      getSrcs(MachineInstr *MI) const;
107
108  unsigned  isLegalUpTo(
109    const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
110    const std::vector<R600InstrInfo::BankSwizzle> &Swz,
111    const std::vector<std::pair<int, unsigned> > &TransSrcs,
112    R600InstrInfo::BankSwizzle TransSwz) const;
113
114  bool FindSwizzleForVectorSlot(
115    const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
116    std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
117    const std::vector<std::pair<int, unsigned> > &TransSrcs,
118    R600InstrInfo::BankSwizzle TransSwz) const;
119
120  /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
121  /// returns true and the first (in lexical order) BankSwizzle affectation
122  /// starting from the one already provided in the Instruction Group MIs that
123  /// fits Read Port limitations in BS if available. Otherwise returns false
124  /// and undefined content in BS.
125  /// isLastAluTrans should be set if the last Alu of MIs will be executed on
126  /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
127  /// apply to the last instruction.
128  /// PV holds GPR to PV registers in the Instruction Group MIs.
129  bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
130                               const DenseMap<unsigned, unsigned> &PV,
131                               std::vector<BankSwizzle> &BS,
132                               bool isLastAluTrans) const;
133
134  /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
135  /// from KCache bank on R700+. This function check if MI set in input meet
136  /// this limitations
137  bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
138  /// Same but using const index set instead of MI set.
139  bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
140
141  /// \brief Vector instructions are instructions that must fill all
142  /// instruction slots within an instruction group.
143  bool isVector(const MachineInstr &MI) const;
144
145  virtual unsigned getIEQOpcode() const;
146  virtual bool isMov(unsigned Opcode) const;
147
148  DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
149                                           const ScheduleDAG *DAG) const;
150
151  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
152
153  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
154                     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
155
156  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
157
158  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
159
160  bool isPredicated(const MachineInstr *MI) const;
161
162  bool isPredicable(MachineInstr *MI) const;
163
164  bool
165   isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
166                             const BranchProbability &Probability) const;
167
168  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
169                           unsigned ExtraPredCycles,
170                           const BranchProbability &Probability) const ;
171
172  bool
173   isProfitableToIfCvt(MachineBasicBlock &TMBB,
174                       unsigned NumTCycles, unsigned ExtraTCycles,
175                       MachineBasicBlock &FMBB,
176                       unsigned NumFCycles, unsigned ExtraFCycles,
177                       const BranchProbability &Probability) const;
178
179  bool DefinesPredicate(MachineInstr *MI,
180                                  std::vector<MachineOperand> &Pred) const;
181
182  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
183                         const SmallVectorImpl<MachineOperand> &Pred2) const;
184
185  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
186                                          MachineBasicBlock &FMBB) const;
187
188  bool PredicateInstruction(MachineInstr *MI,
189                        const SmallVectorImpl<MachineOperand> &Pred) const;
190
191  unsigned int getPredicationCost(const MachineInstr *) const;
192
193  unsigned int getInstrLatency(const InstrItineraryData *ItinData,
194                               const MachineInstr *MI,
195                               unsigned *PredCost = 0) const;
196
197  virtual int getInstrLatency(const InstrItineraryData *ItinData,
198                              SDNode *Node) const { return 1;}
199
200  /// \brief Reserve the registers that may be accesed using indirect addressing.
201  void reserveIndirectRegisters(BitVector &Reserved,
202                                const MachineFunction &MF) const;
203
204  virtual unsigned calculateIndirectAddress(unsigned RegIndex,
205                                            unsigned Channel) const;
206
207  virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
208
209  virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
210                                  MachineBasicBlock::iterator I,
211                                  unsigned ValueReg, unsigned Address,
212                                  unsigned OffsetReg) const;
213
214  virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
215                                  MachineBasicBlock::iterator I,
216                                  unsigned ValueReg, unsigned Address,
217                                  unsigned OffsetReg) const;
218
219  unsigned getMaxAlusPerClause() const;
220
221  ///buildDefaultInstruction - This function returns a MachineInstr with
222  /// all the instruction modifiers initialized to their default values.
223  /// You can use this function to avoid manually specifying each instruction
224  /// modifier operand when building a new instruction.
225  ///
226  /// \returns a MachineInstr with all the instruction modifiers initialized
227  /// to their default values.
228  MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
229                                              MachineBasicBlock::iterator I,
230                                              unsigned Opcode,
231                                              unsigned DstReg,
232                                              unsigned Src0Reg,
233                                              unsigned Src1Reg = 0) const;
234
235  MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
236                                             MachineInstr *MI,
237                                             unsigned Slot,
238                                             unsigned DstReg) const;
239
240  MachineInstr *buildMovImm(MachineBasicBlock &BB,
241                                  MachineBasicBlock::iterator I,
242                                  unsigned DstReg,
243                                  uint64_t Imm) const;
244
245  MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
246                              MachineBasicBlock::iterator I,
247                              unsigned DstReg, unsigned SrcReg) const;
248
249  /// \brief Get the index of Op in the MachineInstr.
250  ///
251  /// \returns -1 if the Instruction does not contain the specified \p Op.
252  int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
253
254  /// \brief Get the index of \p Op for the given Opcode.
255  ///
256  /// \returns -1 if the Instruction does not contain the specified \p Op.
257  int getOperandIdx(unsigned Opcode, unsigned Op) const;
258
259  /// \brief Helper function for setting instruction flag values.
260  void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
261
262  /// \returns true if this instruction has an operand for storing target flags.
263  bool hasFlagOperand(const MachineInstr &MI) const;
264
265  ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
266  void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
267
268  ///\brief Determine if the specified \p Flag is set on this \p Operand.
269  bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
270
271  /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
272  /// \param Flag The flag being set.
273  ///
274  /// \returns the operand containing the flags for this instruction.
275  MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
276                            unsigned Flag = 0) const;
277
278  /// \brief Clear the specified flag on the instruction.
279  void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
280};
281
282namespace AMDGPU {
283
284int getLDSNoRetOp(uint16_t Opcode);
285
286} //End namespace AMDGPU
287
288} // End llvm namespace
289
290#endif // R600INSTRINFO_H_
291