R600InstrInfo.h revision a2b4eb6d15a13de257319ac6231b5ab622cd02b1
1//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10/// \file 11/// \brief Interface definition for R600InstrInfo 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef R600INSTRUCTIONINFO_H_ 16#define R600INSTRUCTIONINFO_H_ 17 18#include "AMDGPUInstrInfo.h" 19#include "R600Defines.h" 20#include "R600RegisterInfo.h" 21#include <map> 22 23namespace llvm { 24 25 class AMDGPUTargetMachine; 26 class DFAPacketizer; 27 class ScheduleDAG; 28 class MachineFunction; 29 class MachineInstr; 30 class MachineInstrBuilder; 31 32 class R600InstrInfo : public AMDGPUInstrInfo { 33 private: 34 const R600RegisterInfo RI; 35 const AMDGPUSubtarget &ST; 36 37 int getBranchInstr(const MachineOperand &op) const; 38 std::vector<std::pair<int, unsigned> > 39 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const; 40 41 public: 42 enum BankSwizzle { 43 ALU_VEC_012_SCL_210 = 0, 44 ALU_VEC_021_SCL_122, 45 ALU_VEC_120_SCL_212, 46 ALU_VEC_102_SCL_221, 47 ALU_VEC_201, 48 ALU_VEC_210 49 }; 50 51 explicit R600InstrInfo(AMDGPUTargetMachine &tm); 52 53 const R600RegisterInfo &getRegisterInfo() const; 54 virtual void copyPhysReg(MachineBasicBlock &MBB, 55 MachineBasicBlock::iterator MI, DebugLoc DL, 56 unsigned DestReg, unsigned SrcReg, 57 bool KillSrc) const; 58 59 bool isTrig(const MachineInstr &MI) const; 60 bool isPlaceHolderOpcode(unsigned opcode) const; 61 bool isReductionOp(unsigned opcode) const; 62 bool isCubeOp(unsigned opcode) const; 63 64 /// \returns true if this \p Opcode represents an ALU instruction. 65 bool isALUInstr(unsigned Opcode) const; 66 bool hasInstrModifiers(unsigned Opcode) const; 67 bool isLDSInstr(unsigned Opcode) const; 68 69 /// \returns true if this \p Opcode represents an ALU instruction or an 70 /// instruction that will be lowered in ExpandSpecialInstrs Pass. 71 bool canBeConsideredALU(const MachineInstr *MI) const; 72 73 bool isTransOnly(unsigned Opcode) const; 74 bool isTransOnly(const MachineInstr *MI) const; 75 bool isVectorOnly(unsigned Opcode) const; 76 bool isVectorOnly(const MachineInstr *MI) const; 77 bool isExport(unsigned Opcode) const; 78 79 bool usesVertexCache(unsigned Opcode) const; 80 bool usesVertexCache(const MachineInstr *MI) const; 81 bool usesTextureCache(unsigned Opcode) const; 82 bool usesTextureCache(const MachineInstr *MI) const; 83 84 bool mustBeLastInClause(unsigned Opcode) const; 85 bool usesAddressRegister(MachineInstr *MI) const; 86 bool definesAddressRegister(MachineInstr *MI) const; 87 bool readsLDSSrcReg(const MachineInstr *MI) const; 88 89 /// \returns The operand index for the given source number. Legal values 90 /// for SrcNum are 0, 1, and 2. 91 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const; 92 /// \returns The operand Index for the Sel operand given an index to one 93 /// of the instruction's src operands. 94 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const; 95 96 /// \returns a pair for each src of an ALU instructions. 97 /// The first member of a pair is the register id. 98 /// If register is ALU_CONST, second member is SEL. 99 /// If register is ALU_LITERAL, second member is IMM. 100 /// Otherwise, second member value is undefined. 101 SmallVector<std::pair<MachineOperand *, int64_t>, 3> 102 getSrcs(MachineInstr *MI) const; 103 104 unsigned isLegalUpTo( 105 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, 106 const std::vector<R600InstrInfo::BankSwizzle> &Swz, 107 const std::vector<std::pair<int, unsigned> > &TransSrcs, 108 R600InstrInfo::BankSwizzle TransSwz) const; 109 110 bool FindSwizzleForVectorSlot( 111 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, 112 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, 113 const std::vector<std::pair<int, unsigned> > &TransSrcs, 114 R600InstrInfo::BankSwizzle TransSwz) const; 115 116 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 117 /// returns true and the first (in lexical order) BankSwizzle affectation 118 /// starting from the one already provided in the Instruction Group MIs that 119 /// fits Read Port limitations in BS if available. Otherwise returns false 120 /// and undefined content in BS. 121 /// isLastAluTrans should be set if the last Alu of MIs will be executed on 122 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to 123 /// apply to the last instruction. 124 /// PV holds GPR to PV registers in the Instruction Group MIs. 125 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs, 126 const DenseMap<unsigned, unsigned> &PV, 127 std::vector<BankSwizzle> &BS, 128 bool isLastAluTrans) const; 129 130 /// An instruction group can only access 2 channel pair (either [XY] or [ZW]) 131 /// from KCache bank on R700+. This function check if MI set in input meet 132 /// this limitations 133 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const; 134 /// Same but using const index set instead of MI set. 135 bool fitsConstReadLimitations(const std::vector<unsigned>&) const; 136 137 /// \breif Vector instructions are instructions that must fill all 138 /// instruction slots within an instruction group. 139 bool isVector(const MachineInstr &MI) const; 140 141 virtual unsigned getIEQOpcode() const; 142 virtual bool isMov(unsigned Opcode) const; 143 144 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM, 145 const ScheduleDAG *DAG) const; 146 147 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 148 149 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 150 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const; 151 152 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const; 153 154 unsigned RemoveBranch(MachineBasicBlock &MBB) const; 155 156 bool isPredicated(const MachineInstr *MI) const; 157 158 bool isPredicable(MachineInstr *MI) const; 159 160 bool 161 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 162 const BranchProbability &Probability) const; 163 164 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 165 unsigned ExtraPredCycles, 166 const BranchProbability &Probability) const ; 167 168 bool 169 isProfitableToIfCvt(MachineBasicBlock &TMBB, 170 unsigned NumTCycles, unsigned ExtraTCycles, 171 MachineBasicBlock &FMBB, 172 unsigned NumFCycles, unsigned ExtraFCycles, 173 const BranchProbability &Probability) const; 174 175 bool DefinesPredicate(MachineInstr *MI, 176 std::vector<MachineOperand> &Pred) const; 177 178 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 179 const SmallVectorImpl<MachineOperand> &Pred2) const; 180 181 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 182 MachineBasicBlock &FMBB) const; 183 184 bool PredicateInstruction(MachineInstr *MI, 185 const SmallVectorImpl<MachineOperand> &Pred) const; 186 187 unsigned int getPredicationCost(const MachineInstr *) const; 188 189 unsigned int getInstrLatency(const InstrItineraryData *ItinData, 190 const MachineInstr *MI, 191 unsigned *PredCost = 0) const; 192 193 virtual int getInstrLatency(const InstrItineraryData *ItinData, 194 SDNode *Node) const { return 1;} 195 196 /// \brief Reserve the registers that may be accesed using indirect addressing. 197 void reserveIndirectRegisters(BitVector &Reserved, 198 const MachineFunction &MF) const; 199 200 virtual unsigned calculateIndirectAddress(unsigned RegIndex, 201 unsigned Channel) const; 202 203 virtual const TargetRegisterClass *getIndirectAddrRegClass() const; 204 205 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 206 MachineBasicBlock::iterator I, 207 unsigned ValueReg, unsigned Address, 208 unsigned OffsetReg) const; 209 210 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 211 MachineBasicBlock::iterator I, 212 unsigned ValueReg, unsigned Address, 213 unsigned OffsetReg) const; 214 215 unsigned getMaxAlusPerClause() const; 216 217 ///buildDefaultInstruction - This function returns a MachineInstr with 218 /// all the instruction modifiers initialized to their default values. 219 /// You can use this function to avoid manually specifying each instruction 220 /// modifier operand when building a new instruction. 221 /// 222 /// \returns a MachineInstr with all the instruction modifiers initialized 223 /// to their default values. 224 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, 225 MachineBasicBlock::iterator I, 226 unsigned Opcode, 227 unsigned DstReg, 228 unsigned Src0Reg, 229 unsigned Src1Reg = 0) const; 230 231 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB, 232 MachineInstr *MI, 233 unsigned Slot, 234 unsigned DstReg) const; 235 236 MachineInstr *buildMovImm(MachineBasicBlock &BB, 237 MachineBasicBlock::iterator I, 238 unsigned DstReg, 239 uint64_t Imm) const; 240 241 MachineInstr *buildMovInstr(MachineBasicBlock *MBB, 242 MachineBasicBlock::iterator I, 243 unsigned DstReg, unsigned SrcReg) const; 244 245 /// \brief Get the index of Op in the MachineInstr. 246 /// 247 /// \returns -1 if the Instruction does not contain the specified \p Op. 248 int getOperandIdx(const MachineInstr &MI, unsigned Op) const; 249 250 /// \brief Get the index of \p Op for the given Opcode. 251 /// 252 /// \returns -1 if the Instruction does not contain the specified \p Op. 253 int getOperandIdx(unsigned Opcode, unsigned Op) const; 254 255 /// \brief Helper function for setting instruction flag values. 256 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const; 257 258 /// \returns true if this instruction has an operand for storing target flags. 259 bool hasFlagOperand(const MachineInstr &MI) const; 260 261 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand. 262 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 263 264 ///\brief Determine if the specified \p Flag is set on this \p Operand. 265 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const; 266 267 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2) 268 /// \param Flag The flag being set. 269 /// 270 /// \returns the operand containing the flags for this instruction. 271 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0, 272 unsigned Flag = 0) const; 273 274 /// \brief Clear the specified flag on the instruction. 275 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 276}; 277 278namespace AMDGPU { 279 280int getLDSNoRetOp(uint16_t Opcode); 281 282} //End namespace AMDGPU 283 284} // End llvm namespace 285 286#endif // R600INSTRINFO_H_ 287