R600Instructions.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// TableGen definitions for instructions which are available on R600 family 11// GPUs. 12// 13//===----------------------------------------------------------------------===// 14 15include "R600Intrinsics.td" 16include "R600InstrFormats.td" 17 18class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> : 19 InstR600 <outs, ins, asm, pattern, NullALU> { 20 21 let Namespace = "AMDGPU"; 22} 23 24def MEMxi : Operand<iPTR> { 25 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 26 let PrintMethod = "printMemOperand"; 27} 28 29def MEMrr : Operand<iPTR> { 30 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 31} 32 33// Operands for non-registers 34 35class InstFlag<string PM = "printOperand", int Default = 0> 36 : OperandWithDefaultOps <i32, (ops (i32 Default))> { 37 let PrintMethod = PM; 38} 39 40// src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers 41def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> { 42 let PrintMethod = "printSel"; 43} 44def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> { 45 let PrintMethod = "printBankSwizzle"; 46} 47 48def LITERAL : InstFlag<"printLiteral">; 49 50def WRITE : InstFlag <"printWrite", 1>; 51def OMOD : InstFlag <"printOMOD">; 52def REL : InstFlag <"printRel">; 53def CLAMP : InstFlag <"printClamp">; 54def NEG : InstFlag <"printNeg">; 55def ABS : InstFlag <"printAbs">; 56def UEM : InstFlag <"printUpdateExecMask">; 57def UP : InstFlag <"printUpdatePred">; 58 59// XXX: The r600g finalizer in Mesa expects last to be one in most cases. 60// Once we start using the packetizer in this backend we should have this 61// default to 0. 62def LAST : InstFlag<"printLast", 1>; 63def RSel : Operand<i32> { 64 let PrintMethod = "printRSel"; 65} 66def CT: Operand<i32> { 67 let PrintMethod = "printCT"; 68} 69 70def FRAMEri : Operand<iPTR> { 71 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index); 72} 73 74def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; 75def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; 76def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; 77def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>; 78def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>; 79 80 81def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), 82 (ops PRED_SEL_OFF)>; 83 84 85let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 86 87// Class for instructions with only one source register. 88// If you add new ins to this instruction, make sure they are listed before 89// $literal, because the backend currently assumes that the last operand is 90// a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in 91// R600Defines.h, R600InstrInfo::buildDefaultInstruction(), 92// and R600InstrInfo::getOperandIdx(). 93class R600_1OP <bits<11> inst, string opName, list<dag> pattern, 94 InstrItinClass itin = AnyALU> : 95 InstR600 <(outs R600_Reg32:$dst), 96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 99 BANK_SWIZZLE:$bank_swizzle), 100 !strconcat(" ", opName, 101 "$clamp $last $dst$write$dst_rel$omod, " 102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 103 "$pred_sel $bank_swizzle"), 104 pattern, 105 itin>, 106 R600ALU_Word0, 107 R600ALU_Word1_OP2 <inst> { 108 109 let src1 = 0; 110 let src1_rel = 0; 111 let src1_neg = 0; 112 let src1_abs = 0; 113 let update_exec_mask = 0; 114 let update_pred = 0; 115 let HasNativeOperands = 1; 116 let Op1 = 1; 117 let ALUInst = 1; 118 let DisableEncoding = "$literal"; 119 let UseNamedOperandTable = 1; 120 121 let Inst{31-0} = Word0; 122 let Inst{63-32} = Word1; 123} 124 125class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node, 126 InstrItinClass itin = AnyALU> : 127 R600_1OP <inst, opName, 128 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))] 129>; 130 131// If you add or change the operands for R600_2OP instructions, you must 132// also update the R600Op2OperandIndex::ROI enum in R600Defines.h, 133// R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx(). 134class R600_2OP <bits<11> inst, string opName, list<dag> pattern, 135 InstrItinClass itin = AnyALU> : 136 InstR600 <(outs R600_Reg32:$dst), 137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write, 138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel, 141 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 142 BANK_SWIZZLE:$bank_swizzle), 143 !strconcat(" ", opName, 144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, " 145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, " 147 "$pred_sel $bank_swizzle"), 148 pattern, 149 itin>, 150 R600ALU_Word0, 151 R600ALU_Word1_OP2 <inst> { 152 153 let HasNativeOperands = 1; 154 let Op2 = 1; 155 let ALUInst = 1; 156 let DisableEncoding = "$literal"; 157 let UseNamedOperandTable = 1; 158 159 let Inst{31-0} = Word0; 160 let Inst{63-32} = Word1; 161} 162 163class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node, 164 InstrItinClass itim = AnyALU> : 165 R600_2OP <inst, opName, 166 [(set R600_Reg32:$dst, (node R600_Reg32:$src0, 167 R600_Reg32:$src1))] 168>; 169 170// If you add our change the operands for R600_3OP instructions, you must 171// also update the R600Op3OperandIndex::ROI enum in R600Defines.h, 172// R600InstrInfo::buildDefaultInstruction(), and 173// R600InstrInfo::getOperandIdx(). 174class R600_3OP <bits<5> inst, string opName, list<dag> pattern, 175 InstrItinClass itin = AnyALU> : 176 InstR600 <(outs R600_Reg32:$dst), 177 (ins REL:$dst_rel, CLAMP:$clamp, 178 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel, 179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel, 180 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel, 181 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 182 BANK_SWIZZLE:$bank_swizzle), 183 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, " 184 "$src0_neg$src0$src0_rel, " 185 "$src1_neg$src1$src1_rel, " 186 "$src2_neg$src2$src2_rel, " 187 "$pred_sel" 188 "$bank_swizzle"), 189 pattern, 190 itin>, 191 R600ALU_Word0, 192 R600ALU_Word1_OP3<inst>{ 193 194 let HasNativeOperands = 1; 195 let DisableEncoding = "$literal"; 196 let Op3 = 1; 197 let UseNamedOperandTable = 1; 198 let ALUInst = 1; 199 200 let Inst{31-0} = Word0; 201 let Inst{63-32} = Word1; 202} 203 204class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern, 205 InstrItinClass itin = VecALU> : 206 InstR600 <(outs R600_Reg32:$dst), 207 ins, 208 asm, 209 pattern, 210 itin>; 211 212 213 214} // End mayLoad = 1, mayStore = 0, hasSideEffects = 0 215 216def TEX_SHADOW : PatLeaf< 217 (imm), 218 [{uint32_t TType = (uint32_t)N->getZExtValue(); 219 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13); 220 }] 221>; 222 223def TEX_RECT : PatLeaf< 224 (imm), 225 [{uint32_t TType = (uint32_t)N->getZExtValue(); 226 return TType == 5; 227 }] 228>; 229 230def TEX_ARRAY : PatLeaf< 231 (imm), 232 [{uint32_t TType = (uint32_t)N->getZExtValue(); 233 return TType == 9 || TType == 10 || TType == 16; 234 }] 235>; 236 237def TEX_SHADOW_ARRAY : PatLeaf< 238 (imm), 239 [{uint32_t TType = (uint32_t)N->getZExtValue(); 240 return TType == 11 || TType == 12 || TType == 17; 241 }] 242>; 243 244def TEX_MSAA : PatLeaf< 245 (imm), 246 [{uint32_t TType = (uint32_t)N->getZExtValue(); 247 return TType == 14; 248 }] 249>; 250 251def TEX_ARRAY_MSAA : PatLeaf< 252 (imm), 253 [{uint32_t TType = (uint32_t)N->getZExtValue(); 254 return TType == 15; 255 }] 256>; 257 258class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask, 259 dag outs, dag ins, string asm, list<dag> pattern> : 260 InstR600ISA <outs, ins, asm, pattern>, 261 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF { 262 263 let rat_id = ratid; 264 let rat_inst = ratinst; 265 let rim = 0; 266 // XXX: Have a separate instruction for non-indexed writes. 267 let type = 1; 268 let rw_rel = 0; 269 let elem_size = 0; 270 271 let array_size = 0; 272 let comp_mask = mask; 273 let burst_count = 0; 274 let vpm = 0; 275 let cf_inst = cfinst; 276 let mark = 0; 277 let barrier = 1; 278 279 let Inst{31-0} = Word0; 280 let Inst{63-32} = Word1; 281 let IsExport = 1; 282 283} 284 285class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 286 : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>, 287 VTX_WORD1_GPR { 288 289 // Static fields 290 let DST_REL = 0; 291 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, 292 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, 293 // however, based on my testing if USE_CONST_FIELDS is set, then all 294 // these fields need to be set to 0. 295 let USE_CONST_FIELDS = 0; 296 let NUM_FORMAT_ALL = 1; 297 let FORMAT_COMP_ALL = 0; 298 let SRF_MODE_ALL = 0; 299 300 let Inst{63-32} = Word1; 301 // LLVM can only encode 64-bit instructions, so these fields are manually 302 // encoded in R600CodeEmitter 303 // 304 // bits<16> OFFSET; 305 // bits<2> ENDIAN_SWAP = 0; 306 // bits<1> CONST_BUF_NO_STRIDE = 0; 307 // bits<1> MEGA_FETCH = 0; 308 // bits<1> ALT_CONST = 0; 309 // bits<2> BUFFER_INDEX_MODE = 0; 310 311 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 312 // is done in R600CodeEmitter 313 // 314 // Inst{79-64} = OFFSET; 315 // Inst{81-80} = ENDIAN_SWAP; 316 // Inst{82} = CONST_BUF_NO_STRIDE; 317 // Inst{83} = MEGA_FETCH; 318 // Inst{84} = ALT_CONST; 319 // Inst{86-85} = BUFFER_INDEX_MODE; 320 // Inst{95-86} = 0; Reserved 321 322 // VTX_WORD3 (Padding) 323 // 324 // Inst{127-96} = 0; 325 326 let VTXInst = 1; 327} 328 329class LoadParamFrag <PatFrag load_type> : PatFrag < 330 (ops node:$ptr), (load_type node:$ptr), 331 [{ return isConstantLoad(dyn_cast<LoadSDNode>(N), 0); }] 332>; 333 334def load_param : LoadParamFrag<load>; 335def load_param_exti8 : LoadParamFrag<az_extloadi8>; 336def load_param_exti16 : LoadParamFrag<az_extloadi16>; 337 338def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">; 339 340def isR600toCayman : Predicate< 341 "Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">; 342 343//===----------------------------------------------------------------------===// 344// R600 SDNodes 345//===----------------------------------------------------------------------===// 346 347def INTERP_PAIR_XY : AMDGPUShaderInst < 348 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1), 349 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 350 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1", 351 []>; 352 353def INTERP_PAIR_ZW : AMDGPUShaderInst < 354 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1), 355 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 356 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1", 357 []>; 358 359def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS", 360 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>, 361 [SDNPVariadic] 362>; 363 364def DOT4 : SDNode<"AMDGPUISD::DOT4", 365 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, 366 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>, 367 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>, 368 [] 369>; 370 371def COS_HW : SDNode<"AMDGPUISD::COS_HW", 372 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 373>; 374 375def SIN_HW : SDNode<"AMDGPUISD::SIN_HW", 376 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 377>; 378 379def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>; 380 381def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>; 382 383multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> { 384def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR, 385 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw), 386 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz), 387 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z), 388 (i32 imm:$DST_SEL_W), 389 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID), 390 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z), 391 (i32 imm:$COORD_TYPE_W)), 392 (inst R600_Reg128:$SRC_GPR, 393 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw, 394 imm:$offsetx, imm:$offsety, imm:$offsetz, 395 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z, 396 imm:$DST_SEL_W, 397 imm:$RESOURCE_ID, imm:$SAMPLER_ID, 398 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z, 399 imm:$COORD_TYPE_W)>; 400} 401 402//===----------------------------------------------------------------------===// 403// Interpolation Instructions 404//===----------------------------------------------------------------------===// 405 406def INTERP_VEC_LOAD : AMDGPUShaderInst < 407 (outs R600_Reg128:$dst), 408 (ins i32imm:$src0), 409 "INTERP_LOAD $src0 : $dst", 410 [(set R600_Reg128:$dst, (int_R600_interp_const imm:$src0))]>; 411 412def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> { 413 let bank_swizzle = 5; 414} 415 416def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> { 417 let bank_swizzle = 5; 418} 419 420def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>; 421 422//===----------------------------------------------------------------------===// 423// Export Instructions 424//===----------------------------------------------------------------------===// 425 426def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>; 427 428def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType, 429 [SDNPHasChain, SDNPSideEffect]>; 430 431class ExportWord0 { 432 field bits<32> Word0; 433 434 bits<13> arraybase; 435 bits<2> type; 436 bits<7> gpr; 437 bits<2> elem_size; 438 439 let Word0{12-0} = arraybase; 440 let Word0{14-13} = type; 441 let Word0{21-15} = gpr; 442 let Word0{22} = 0; // RW_REL 443 let Word0{29-23} = 0; // INDEX_GPR 444 let Word0{31-30} = elem_size; 445} 446 447class ExportSwzWord1 { 448 field bits<32> Word1; 449 450 bits<3> sw_x; 451 bits<3> sw_y; 452 bits<3> sw_z; 453 bits<3> sw_w; 454 bits<1> eop; 455 bits<8> inst; 456 457 let Word1{2-0} = sw_x; 458 let Word1{5-3} = sw_y; 459 let Word1{8-6} = sw_z; 460 let Word1{11-9} = sw_w; 461} 462 463class ExportBufWord1 { 464 field bits<32> Word1; 465 466 bits<12> arraySize; 467 bits<4> compMask; 468 bits<1> eop; 469 bits<8> inst; 470 471 let Word1{11-0} = arraySize; 472 let Word1{15-12} = compMask; 473} 474 475multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> { 476 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg), 477 (ExportInst 478 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0), 479 0, 61, 0, 7, 7, 7, cf_inst, 0) 480 >; 481 482 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg), 483 (ExportInst 484 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0), 485 0, 61, 7, 0, 7, 7, cf_inst, 0) 486 >; 487 488 def : Pat<(int_R600_store_dummy (i32 imm:$type)), 489 (ExportInst 490 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0) 491 >; 492 493 def : Pat<(int_R600_store_dummy 1), 494 (ExportInst 495 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0) 496 >; 497 498 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type), 499 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)), 500 (ExportInst R600_Reg128:$src, imm:$type, imm:$base, 501 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0) 502 >; 503 504} 505 506multiclass SteamOutputExportPattern<Instruction ExportInst, 507 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> { 508// Stream0 509 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 510 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)), 511 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 512 4095, imm:$mask, buf0inst, 0)>; 513// Stream1 514 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 515 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)), 516 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 517 4095, imm:$mask, buf1inst, 0)>; 518// Stream2 519 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 520 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)), 521 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 522 4095, imm:$mask, buf2inst, 0)>; 523// Stream3 524 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 525 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)), 526 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 527 4095, imm:$mask, buf3inst, 0)>; 528} 529 530// Export Instructions should not be duplicated by TailDuplication pass 531// (which assumes that duplicable instruction are affected by exec mask) 532let usesCustomInserter = 1, isNotDuplicable = 1 in { 533 534class ExportSwzInst : InstR600ISA<( 535 outs), 536 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 537 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst, 538 i32imm:$eop), 539 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"), 540 []>, ExportWord0, ExportSwzWord1 { 541 let elem_size = 3; 542 let Inst{31-0} = Word0; 543 let Inst{63-32} = Word1; 544 let IsExport = 1; 545} 546 547} // End usesCustomInserter = 1 548 549class ExportBufInst : InstR600ISA<( 550 outs), 551 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 552 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop), 553 !strconcat("EXPORT", " $gpr"), 554 []>, ExportWord0, ExportBufWord1 { 555 let elem_size = 0; 556 let Inst{31-0} = Word0; 557 let Inst{63-32} = Word1; 558 let IsExport = 1; 559} 560 561//===----------------------------------------------------------------------===// 562// Control Flow Instructions 563//===----------------------------------------------------------------------===// 564 565 566def KCACHE : InstFlag<"printKCache">; 567 568class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs), 569(ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, 570KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1, 571i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, 572i32imm:$COUNT, i32imm:$Enabled), 573!strconcat(OpName, " $COUNT, @$ADDR, " 574"KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"), 575[] >, CF_ALU_WORD0, CF_ALU_WORD1 { 576 field bits<64> Inst; 577 578 let CF_INST = inst; 579 let ALT_CONST = 0; 580 let WHOLE_QUAD_MODE = 0; 581 let BARRIER = 1; 582 let UseNamedOperandTable = 1; 583 584 let Inst{31-0} = Word0; 585 let Inst{63-32} = Word1; 586} 587 588class CF_WORD0_R600 { 589 field bits<32> Word0; 590 591 bits<32> ADDR; 592 593 let Word0 = ADDR; 594} 595 596class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs), 597ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 { 598 field bits<64> Inst; 599 bits<4> CNT; 600 601 let CF_INST = inst; 602 let BARRIER = 1; 603 let CF_CONST = 0; 604 let VALID_PIXEL_MODE = 0; 605 let COND = 0; 606 let COUNT = CNT{2-0}; 607 let CALL_COUNT = 0; 608 let COUNT_3 = CNT{3}; 609 let END_OF_PROGRAM = 0; 610 let WHOLE_QUAD_MODE = 0; 611 612 let Inst{31-0} = Word0; 613 let Inst{63-32} = Word1; 614} 615 616class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs), 617ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG { 618 field bits<64> Inst; 619 620 let CF_INST = inst; 621 let BARRIER = 1; 622 let JUMPTABLE_SEL = 0; 623 let CF_CONST = 0; 624 let VALID_PIXEL_MODE = 0; 625 let COND = 0; 626 let END_OF_PROGRAM = 0; 627 628 let Inst{31-0} = Word0; 629 let Inst{63-32} = Word1; 630} 631 632def CF_ALU : ALU_CLAUSE<8, "ALU">; 633def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">; 634def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">; 635def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">; 636def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">; 637def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">; 638 639def FETCH_CLAUSE : AMDGPUInst <(outs), 640(ins i32imm:$addr), "Fetch clause starting at $addr:", [] > { 641 field bits<8> Inst; 642 bits<8> num; 643 let Inst = num; 644} 645 646def ALU_CLAUSE : AMDGPUInst <(outs), 647(ins i32imm:$addr), "ALU clause starting at $addr:", [] > { 648 field bits<8> Inst; 649 bits<8> num; 650 let Inst = num; 651} 652 653def LITERALS : AMDGPUInst <(outs), 654(ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > { 655 field bits<64> Inst; 656 bits<32> literal1; 657 bits<32> literal2; 658 659 let Inst{31-0} = literal1; 660 let Inst{63-32} = literal2; 661} 662 663def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > { 664 field bits<64> Inst; 665} 666 667let Predicates = [isR600toCayman] in { 668 669//===----------------------------------------------------------------------===// 670// Common Instructions R600, R700, Evergreen, Cayman 671//===----------------------------------------------------------------------===// 672 673def ADD : R600_2OP_Helper <0x0, "ADD", fadd>; 674// Non-IEEE MUL: 0 * anything = 0 675def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>; 676def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>; 677def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>; 678def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>; 679 680// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, 681// so some of the instruction names don't match the asm string. 682// XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. 683def SETE : R600_2OP < 684 0x08, "SETE", 685 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))] 686>; 687 688def SGT : R600_2OP < 689 0x09, "SETGT", 690 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))] 691>; 692 693def SGE : R600_2OP < 694 0xA, "SETGE", 695 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))] 696>; 697 698def SNE : R600_2OP < 699 0xB, "SETNE", 700 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE))] 701>; 702 703def SETE_DX10 : R600_2OP < 704 0xC, "SETE_DX10", 705 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))] 706>; 707 708def SETGT_DX10 : R600_2OP < 709 0xD, "SETGT_DX10", 710 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))] 711>; 712 713def SETGE_DX10 : R600_2OP < 714 0xE, "SETGE_DX10", 715 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))] 716>; 717 718def SETNE_DX10 : R600_2OP < 719 0xF, "SETNE_DX10", 720 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE))] 721>; 722 723def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>; 724def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>; 725def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>; 726def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>; 727def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>; 728 729// Add also ftrunc intrinsic pattern 730def : Pat<(ftrunc f32:$src0), (TRUNC $src0)>; 731 732def MOV : R600_1OP <0x19, "MOV", []>; 733 734let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { 735 736class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst < 737 (outs R600_Reg32:$dst), 738 (ins immType:$imm), 739 "", 740 [] 741>; 742 743} // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 744 745def MOV_IMM_I32 : MOV_IMM<i32, i32imm>; 746def : Pat < 747 (imm:$val), 748 (MOV_IMM_I32 imm:$val) 749>; 750 751def MOV_IMM_F32 : MOV_IMM<f32, f32imm>; 752def : Pat < 753 (fpimm:$val), 754 (MOV_IMM_F32 fpimm:$val) 755>; 756 757def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>; 758def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>; 759def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>; 760def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>; 761 762let hasSideEffects = 1 in { 763 764def KILLGT : R600_2OP <0x2D, "KILLGT", []>; 765 766} // end hasSideEffects 767 768def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>; 769def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>; 770def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>; 771def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>; 772def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>; 773def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>; 774def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>; 775def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>; 776def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>; 777def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>; 778 779def SETE_INT : R600_2OP < 780 0x3A, "SETE_INT", 781 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))] 782>; 783 784def SETGT_INT : R600_2OP < 785 0x3B, "SETGT_INT", 786 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))] 787>; 788 789def SETGE_INT : R600_2OP < 790 0x3C, "SETGE_INT", 791 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))] 792>; 793 794def SETNE_INT : R600_2OP < 795 0x3D, "SETNE_INT", 796 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))] 797>; 798 799def SETGT_UINT : R600_2OP < 800 0x3E, "SETGT_UINT", 801 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))] 802>; 803 804def SETGE_UINT : R600_2OP < 805 0x3F, "SETGE_UINT", 806 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))] 807>; 808 809def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>; 810def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>; 811def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>; 812def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>; 813 814def CNDE_INT : R600_3OP < 815 0x1C, "CNDE_INT", 816 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))] 817>; 818 819def CNDGE_INT : R600_3OP < 820 0x1E, "CNDGE_INT", 821 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))] 822>; 823 824def CNDGT_INT : R600_3OP < 825 0x1D, "CNDGT_INT", 826 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))] 827>; 828 829//===----------------------------------------------------------------------===// 830// Texture instructions 831//===----------------------------------------------------------------------===// 832 833let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 834 835class R600_TEX <bits<11> inst, string opName> : 836 InstR600 <(outs R600_Reg128:$DST_GPR), 837 (ins R600_Reg128:$SRC_GPR, 838 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw, 839 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz, 840 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W, 841 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, 842 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z, 843 CT:$COORD_TYPE_W), 844 !strconcat(opName, 845 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, " 846 "$SRC_GPR.$srcx$srcy$srcz$srcw " 847 "RID:$RESOURCE_ID SID:$SAMPLER_ID " 848 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"), 849 [], 850 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 { 851 let Inst{31-0} = Word0; 852 let Inst{63-32} = Word1; 853 854 let TEX_INST = inst{4-0}; 855 let SRC_REL = 0; 856 let DST_REL = 0; 857 let LOD_BIAS = 0; 858 859 let INST_MOD = 0; 860 let FETCH_WHOLE_QUAD = 0; 861 let ALT_CONST = 0; 862 let SAMPLER_INDEX_MODE = 0; 863 let RESOURCE_INDEX_MODE = 0; 864 865 let TEXInst = 1; 866} 867 868} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 869 870 871 872def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">; 873def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">; 874def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">; 875def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">; 876def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">; 877def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">; 878def TEX_LD : R600_TEX <0x03, "TEX_LD">; 879def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> { 880 let INST_MOD = 1; 881} 882def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">; 883def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">; 884def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">; 885def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">; 886def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">; 887def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">; 888def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">; 889 890defm : TexPattern<0, TEX_SAMPLE>; 891defm : TexPattern<1, TEX_SAMPLE_C>; 892defm : TexPattern<2, TEX_SAMPLE_L>; 893defm : TexPattern<3, TEX_SAMPLE_C_L>; 894defm : TexPattern<4, TEX_SAMPLE_LB>; 895defm : TexPattern<5, TEX_SAMPLE_C_LB>; 896defm : TexPattern<6, TEX_LD, v4i32>; 897defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>; 898defm : TexPattern<8, TEX_GET_GRADIENTS_H>; 899defm : TexPattern<9, TEX_GET_GRADIENTS_V>; 900defm : TexPattern<10, TEX_LDPTR, v4i32>; 901 902//===----------------------------------------------------------------------===// 903// Helper classes for common instructions 904//===----------------------------------------------------------------------===// 905 906class MUL_LIT_Common <bits<5> inst> : R600_3OP < 907 inst, "MUL_LIT", 908 [] 909>; 910 911class MULADD_Common <bits<5> inst> : R600_3OP < 912 inst, "MULADD", 913 [] 914>; 915 916class MULADD_IEEE_Common <bits<5> inst> : R600_3OP < 917 inst, "MULADD_IEEE", 918 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))] 919>; 920 921class CNDE_Common <bits<5> inst> : R600_3OP < 922 inst, "CNDE", 923 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))] 924>; 925 926class CNDGT_Common <bits<5> inst> : R600_3OP < 927 inst, "CNDGT", 928 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))] 929> { 930 let Itinerary = VecALU; 931} 932 933class CNDGE_Common <bits<5> inst> : R600_3OP < 934 inst, "CNDGE", 935 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))] 936> { 937 let Itinerary = VecALU; 938} 939 940 941let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in { 942class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins 943// Slot X 944 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X, 945 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X, 946 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X, 947 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X, 948 R600_Pred:$pred_sel_X, 949// Slot Y 950 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y, 951 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y, 952 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y, 953 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y, 954 R600_Pred:$pred_sel_Y, 955// Slot Z 956 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z, 957 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z, 958 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z, 959 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z, 960 R600_Pred:$pred_sel_Z, 961// Slot W 962 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W, 963 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W, 964 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W, 965 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W, 966 R600_Pred:$pred_sel_W, 967 LITERAL:$literal0, LITERAL:$literal1), 968 "", 969 pattern, 970 AnyALU> { 971 972 let UseNamedOperandTable = 1; 973 974} 975} 976 977def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4 978 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X, 979 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y, 980 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z, 981 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>; 982 983 984class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>; 985 986 987let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 988multiclass CUBE_Common <bits<11> inst> { 989 990 def _pseudo : InstR600 < 991 (outs R600_Reg128:$dst), 992 (ins R600_Reg128:$src0), 993 "CUBE $dst $src0", 994 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))], 995 VecALU 996 > { 997 let isPseudo = 1; 998 let UseNamedOperandTable = 1; 999 } 1000 1001 def _real : R600_2OP <inst, "CUBE", []>; 1002} 1003} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 1004 1005class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1006 inst, "EXP_IEEE", fexp2 1007> { 1008 let Itinerary = TransALU; 1009} 1010 1011class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper < 1012 inst, "FLT_TO_INT", fp_to_sint 1013> { 1014 let Itinerary = TransALU; 1015} 1016 1017class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1018 inst, "INT_TO_FLT", sint_to_fp 1019> { 1020 let Itinerary = TransALU; 1021} 1022 1023class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1024 inst, "FLT_TO_UINT", fp_to_uint 1025> { 1026 let Itinerary = TransALU; 1027} 1028 1029class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1030 inst, "UINT_TO_FLT", uint_to_fp 1031> { 1032 let Itinerary = TransALU; 1033} 1034 1035class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP < 1036 inst, "LOG_CLAMPED", [] 1037>; 1038 1039class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1040 inst, "LOG_IEEE", flog2 1041> { 1042 let Itinerary = TransALU; 1043} 1044 1045class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>; 1046class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>; 1047class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>; 1048class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper < 1049 inst, "MULHI_INT", mulhs 1050> { 1051 let Itinerary = TransALU; 1052} 1053class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper < 1054 inst, "MULHI", mulhu 1055> { 1056 let Itinerary = TransALU; 1057} 1058class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper < 1059 inst, "MULLO_INT", mul 1060> { 1061 let Itinerary = TransALU; 1062} 1063class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> { 1064 let Itinerary = TransALU; 1065} 1066 1067class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP < 1068 inst, "RECIP_CLAMPED", [] 1069> { 1070 let Itinerary = TransALU; 1071} 1072 1073class RECIP_IEEE_Common <bits<11> inst> : R600_1OP < 1074 inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 1075> { 1076 let Itinerary = TransALU; 1077} 1078 1079class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1080 inst, "RECIP_UINT", AMDGPUurecip 1081> { 1082 let Itinerary = TransALU; 1083} 1084 1085class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper < 1086 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq 1087> { 1088 let Itinerary = TransALU; 1089} 1090 1091class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP < 1092 inst, "RECIPSQRT_IEEE", [] 1093> { 1094 let Itinerary = TransALU; 1095} 1096 1097class SIN_Common <bits<11> inst> : R600_1OP < 1098 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{ 1099 let Trig = 1; 1100 let Itinerary = TransALU; 1101} 1102 1103class COS_Common <bits<11> inst> : R600_1OP < 1104 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> { 1105 let Trig = 1; 1106 let Itinerary = TransALU; 1107} 1108 1109def CLAMP_R600 : CLAMP <R600_Reg32>; 1110def FABS_R600 : FABS<R600_Reg32>; 1111def FNEG_R600 : FNEG<R600_Reg32>; 1112 1113//===----------------------------------------------------------------------===// 1114// Helper patterns for complex intrinsics 1115//===----------------------------------------------------------------------===// 1116 1117multiclass DIV_Common <InstR600 recip_ieee> { 1118def : Pat< 1119 (int_AMDGPU_div f32:$src0, f32:$src1), 1120 (MUL_IEEE $src0, (recip_ieee $src1)) 1121>; 1122 1123def : Pat< 1124 (fdiv f32:$src0, f32:$src1), 1125 (MUL_IEEE $src0, (recip_ieee $src1)) 1126>; 1127} 1128 1129class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> 1130 : Pat < 1131 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w), 1132 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x)) 1133>; 1134 1135// FROUND pattern 1136class FROUNDPat<Instruction CNDGE> : Pat < 1137 (AMDGPUround f32:$x), 1138 (CNDGE (ADD (FNEG_R600 (f32 HALF)), (FRACT $x)), (CEIL $x), (FLOOR $x)) 1139>; 1140 1141 1142//===----------------------------------------------------------------------===// 1143// R600 / R700 Instructions 1144//===----------------------------------------------------------------------===// 1145 1146let Predicates = [isR600] in { 1147 1148 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; 1149 def MULADD_r600 : MULADD_Common<0x10>; 1150 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>; 1151 def CNDE_r600 : CNDE_Common<0x18>; 1152 def CNDGT_r600 : CNDGT_Common<0x19>; 1153 def CNDGE_r600 : CNDGE_Common<0x1A>; 1154 def DOT4_r600 : DOT4_Common<0x50>; 1155 defm CUBE_r600 : CUBE_Common<0x52>; 1156 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; 1157 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; 1158 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; 1159 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; 1160 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; 1161 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; 1162 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; 1163 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; 1164 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; 1165 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; 1166 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; 1167 def SIN_r600 : SIN_Common<0x6E>; 1168 def COS_r600 : COS_Common<0x6F>; 1169 def ASHR_r600 : ASHR_Common<0x70>; 1170 def LSHR_r600 : LSHR_Common<0x71>; 1171 def LSHL_r600 : LSHL_Common<0x72>; 1172 def MULLO_INT_r600 : MULLO_INT_Common<0x73>; 1173 def MULHI_INT_r600 : MULHI_INT_Common<0x74>; 1174 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; 1175 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; 1176 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; 1177 1178 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>; 1179 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>; 1180 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>; 1181 1182 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>; 1183 def : FROUNDPat <CNDGE_r600>; 1184 1185 def R600_ExportSwz : ExportSwzInst { 1186 let Word1{20-17} = 0; // BURST_COUNT 1187 let Word1{21} = eop; 1188 let Word1{22} = 0; // VALID_PIXEL_MODE 1189 let Word1{30-23} = inst; 1190 let Word1{31} = 1; // BARRIER 1191 } 1192 defm : ExportPattern<R600_ExportSwz, 39>; 1193 1194 def R600_ExportBuf : ExportBufInst { 1195 let Word1{20-17} = 0; // BURST_COUNT 1196 let Word1{21} = eop; 1197 let Word1{22} = 0; // VALID_PIXEL_MODE 1198 let Word1{30-23} = inst; 1199 let Word1{31} = 1; // BARRIER 1200 } 1201 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>; 1202 1203 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT), 1204 "TEX $CNT @$ADDR"> { 1205 let POP_COUNT = 0; 1206 } 1207 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT), 1208 "VTX $CNT @$ADDR"> { 1209 let POP_COUNT = 0; 1210 } 1211 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR), 1212 "LOOP_START_DX10 @$ADDR"> { 1213 let POP_COUNT = 0; 1214 let CNT = 0; 1215 } 1216 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 1217 let POP_COUNT = 0; 1218 let CNT = 0; 1219 } 1220 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR), 1221 "LOOP_BREAK @$ADDR"> { 1222 let POP_COUNT = 0; 1223 let CNT = 0; 1224 } 1225 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR), 1226 "CONTINUE @$ADDR"> { 1227 let POP_COUNT = 0; 1228 let CNT = 0; 1229 } 1230 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1231 "JUMP @$ADDR POP:$POP_COUNT"> { 1232 let CNT = 0; 1233 } 1234 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR), 1235 "PUSH_ELSE @$ADDR"> { 1236 let CNT = 0; 1237 } 1238 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1239 "ELSE @$ADDR POP:$POP_COUNT"> { 1240 let CNT = 0; 1241 } 1242 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> { 1243 let ADDR = 0; 1244 let CNT = 0; 1245 let POP_COUNT = 0; 1246 } 1247 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1248 "POP @$ADDR POP:$POP_COUNT"> { 1249 let CNT = 0; 1250 } 1251 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> { 1252 let CNT = 0; 1253 let POP_COUNT = 0; 1254 let ADDR = 0; 1255 let END_OF_PROGRAM = 1; 1256 } 1257 1258} 1259 1260 1261//===----------------------------------------------------------------------===// 1262// Regist loads and stores - for indirect addressing 1263//===----------------------------------------------------------------------===// 1264 1265defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>; 1266 1267 1268//===----------------------------------------------------------------------===// 1269// Branch Instructions 1270//===----------------------------------------------------------------------===// 1271 1272def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src), 1273 "IF_PREDICATE_SET $src", []>; 1274 1275//===----------------------------------------------------------------------===// 1276// Pseudo instructions 1277//===----------------------------------------------------------------------===// 1278 1279let isPseudo = 1 in { 1280 1281def PRED_X : InstR600 < 1282 (outs R600_Predicate_Bit:$dst), 1283 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags), 1284 "", [], NullALU> { 1285 let FlagOperandIdx = 3; 1286} 1287 1288let isTerminator = 1, isBranch = 1 in { 1289def JUMP_COND : InstR600 < 1290 (outs), 1291 (ins brtarget:$target, R600_Predicate_Bit:$p), 1292 "JUMP $target ($p)", 1293 [], AnyALU 1294 >; 1295 1296def JUMP : InstR600 < 1297 (outs), 1298 (ins brtarget:$target), 1299 "JUMP $target", 1300 [], AnyALU 1301 > 1302{ 1303 let isPredicable = 1; 1304 let isBarrier = 1; 1305} 1306 1307} // End isTerminator = 1, isBranch = 1 1308 1309let usesCustomInserter = 1 in { 1310 1311let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in { 1312 1313def MASK_WRITE : AMDGPUShaderInst < 1314 (outs), 1315 (ins R600_Reg32:$src), 1316 "MASK_WRITE $src", 1317 [] 1318>; 1319 1320} // End mayLoad = 0, mayStore = 0, hasSideEffects = 1 1321 1322 1323def TXD: InstR600 < 1324 (outs R600_Reg128:$dst), 1325 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1326 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1327 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", 1328 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2, 1329 imm:$resourceId, imm:$samplerId, imm:$textureTarget))], 1330 NullALU > { 1331 let TEXInst = 1; 1332} 1333 1334def TXD_SHADOW: InstR600 < 1335 (outs R600_Reg128:$dst), 1336 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1337 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1338 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", 1339 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2, 1340 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))], 1341 NullALU 1342> { 1343 let TEXInst = 1; 1344} 1345} // End isPseudo = 1 1346} // End usesCustomInserter = 1 1347 1348//===---------------------------------------------------------------------===// 1349// Return instruction 1350//===---------------------------------------------------------------------===// 1351let isTerminator = 1, isReturn = 1, hasCtrlDep = 1, 1352 usesCustomInserter = 1 in { 1353 def RETURN : ILFormat<(outs), (ins variable_ops), 1354 "RETURN", [(IL_retflag)]>; 1355} 1356 1357 1358//===----------------------------------------------------------------------===// 1359// Constant Buffer Addressing Support 1360//===----------------------------------------------------------------------===// 1361 1362let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in { 1363def CONST_COPY : Instruction { 1364 let OutOperandList = (outs R600_Reg32:$dst); 1365 let InOperandList = (ins i32imm:$src); 1366 let Pattern = 1367 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))]; 1368 let AsmString = "CONST_COPY"; 1369 let neverHasSideEffects = 1; 1370 let isAsCheapAsAMove = 1; 1371 let Itinerary = NullALU; 1372} 1373} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" 1374 1375def TEX_VTX_CONSTBUF : 1376 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr", 1377 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>, 1378 VTX_WORD1_GPR, VTX_WORD0_eg { 1379 1380 let VC_INST = 0; 1381 let FETCH_TYPE = 2; 1382 let FETCH_WHOLE_QUAD = 0; 1383 let SRC_REL = 0; 1384 let SRC_SEL_X = 0; 1385 let DST_REL = 0; 1386 let USE_CONST_FIELDS = 0; 1387 let NUM_FORMAT_ALL = 2; 1388 let FORMAT_COMP_ALL = 1; 1389 let SRF_MODE_ALL = 1; 1390 let MEGA_FETCH_COUNT = 16; 1391 let DST_SEL_X = 0; 1392 let DST_SEL_Y = 1; 1393 let DST_SEL_Z = 2; 1394 let DST_SEL_W = 3; 1395 let DATA_FORMAT = 35; 1396 1397 let Inst{31-0} = Word0; 1398 let Inst{63-32} = Word1; 1399 1400// LLVM can only encode 64-bit instructions, so these fields are manually 1401// encoded in R600CodeEmitter 1402// 1403// bits<16> OFFSET; 1404// bits<2> ENDIAN_SWAP = 0; 1405// bits<1> CONST_BUF_NO_STRIDE = 0; 1406// bits<1> MEGA_FETCH = 0; 1407// bits<1> ALT_CONST = 0; 1408// bits<2> BUFFER_INDEX_MODE = 0; 1409 1410 1411 1412// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1413// is done in R600CodeEmitter 1414// 1415// Inst{79-64} = OFFSET; 1416// Inst{81-80} = ENDIAN_SWAP; 1417// Inst{82} = CONST_BUF_NO_STRIDE; 1418// Inst{83} = MEGA_FETCH; 1419// Inst{84} = ALT_CONST; 1420// Inst{86-85} = BUFFER_INDEX_MODE; 1421// Inst{95-86} = 0; Reserved 1422 1423// VTX_WORD3 (Padding) 1424// 1425// Inst{127-96} = 0; 1426 let VTXInst = 1; 1427} 1428 1429def TEX_VTX_TEXBUF: 1430 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr", 1431 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>, 1432VTX_WORD1_GPR, VTX_WORD0_eg { 1433 1434let VC_INST = 0; 1435let FETCH_TYPE = 2; 1436let FETCH_WHOLE_QUAD = 0; 1437let SRC_REL = 0; 1438let SRC_SEL_X = 0; 1439let DST_REL = 0; 1440let USE_CONST_FIELDS = 1; 1441let NUM_FORMAT_ALL = 0; 1442let FORMAT_COMP_ALL = 0; 1443let SRF_MODE_ALL = 1; 1444let MEGA_FETCH_COUNT = 16; 1445let DST_SEL_X = 0; 1446let DST_SEL_Y = 1; 1447let DST_SEL_Z = 2; 1448let DST_SEL_W = 3; 1449let DATA_FORMAT = 0; 1450 1451let Inst{31-0} = Word0; 1452let Inst{63-32} = Word1; 1453 1454// LLVM can only encode 64-bit instructions, so these fields are manually 1455// encoded in R600CodeEmitter 1456// 1457// bits<16> OFFSET; 1458// bits<2> ENDIAN_SWAP = 0; 1459// bits<1> CONST_BUF_NO_STRIDE = 0; 1460// bits<1> MEGA_FETCH = 0; 1461// bits<1> ALT_CONST = 0; 1462// bits<2> BUFFER_INDEX_MODE = 0; 1463 1464 1465 1466// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1467// is done in R600CodeEmitter 1468// 1469// Inst{79-64} = OFFSET; 1470// Inst{81-80} = ENDIAN_SWAP; 1471// Inst{82} = CONST_BUF_NO_STRIDE; 1472// Inst{83} = MEGA_FETCH; 1473// Inst{84} = ALT_CONST; 1474// Inst{86-85} = BUFFER_INDEX_MODE; 1475// Inst{95-86} = 0; Reserved 1476 1477// VTX_WORD3 (Padding) 1478// 1479// Inst{127-96} = 0; 1480 let VTXInst = 1; 1481} 1482 1483 1484 1485//===--------------------------------------------------------------------===// 1486// Instructions support 1487//===--------------------------------------------------------------------===// 1488//===---------------------------------------------------------------------===// 1489// Custom Inserter for Branches and returns, this eventually will be a 1490// separate pass 1491//===---------------------------------------------------------------------===// 1492let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in { 1493 def BRANCH : ILFormat<(outs), (ins brtarget:$target), 1494 "; Pseudo unconditional branch instruction", 1495 [(br bb:$target)]>; 1496 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>; 1497} 1498 1499//===---------------------------------------------------------------------===// 1500// Flow and Program control Instructions 1501//===---------------------------------------------------------------------===// 1502let isTerminator=1 in { 1503 def SWITCH : ILFormat< (outs), (ins GPRI32:$src), 1504 !strconcat("SWITCH", " $src"), []>; 1505 def CASE : ILFormat< (outs), (ins GPRI32:$src), 1506 !strconcat("CASE", " $src"), []>; 1507 def BREAK : ILFormat< (outs), (ins), 1508 "BREAK", []>; 1509 def CONTINUE : ILFormat< (outs), (ins), 1510 "CONTINUE", []>; 1511 def DEFAULT : ILFormat< (outs), (ins), 1512 "DEFAULT", []>; 1513 def ELSE : ILFormat< (outs), (ins), 1514 "ELSE", []>; 1515 def ENDSWITCH : ILFormat< (outs), (ins), 1516 "ENDSWITCH", []>; 1517 def ENDMAIN : ILFormat< (outs), (ins), 1518 "ENDMAIN", []>; 1519 def END : ILFormat< (outs), (ins), 1520 "END", []>; 1521 def ENDFUNC : ILFormat< (outs), (ins), 1522 "ENDFUNC", []>; 1523 def ENDIF : ILFormat< (outs), (ins), 1524 "ENDIF", []>; 1525 def WHILELOOP : ILFormat< (outs), (ins), 1526 "WHILE", []>; 1527 def ENDLOOP : ILFormat< (outs), (ins), 1528 "ENDLOOP", []>; 1529 def FUNC : ILFormat< (outs), (ins), 1530 "FUNC", []>; 1531 def RETDYN : ILFormat< (outs), (ins), 1532 "RET_DYN", []>; 1533 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1534 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">; 1535 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1536 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">; 1537 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1538 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">; 1539 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1540 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">; 1541 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1542 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">; 1543 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1544 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">; 1545 defm IFC : BranchInstr2<"IFC">; 1546 defm BREAKC : BranchInstr2<"BREAKC">; 1547 defm CONTINUEC : BranchInstr2<"CONTINUEC">; 1548} 1549 1550//===----------------------------------------------------------------------===// 1551// ISel Patterns 1552//===----------------------------------------------------------------------===// 1553 1554// CND*_INT Pattterns for f32 True / False values 1555 1556class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat < 1557 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc), 1558 (cnd $src0, $src1, $src2) 1559>; 1560 1561def : CND_INT_f32 <CNDE_INT, SETEQ>; 1562def : CND_INT_f32 <CNDGT_INT, SETGT>; 1563def : CND_INT_f32 <CNDGE_INT, SETGE>; 1564 1565//CNDGE_INT extra pattern 1566def : Pat < 1567 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT), 1568 (CNDGE_INT $src0, $src1, $src2) 1569>; 1570 1571// KIL Patterns 1572def KILP : Pat < 1573 (int_AMDGPU_kilp), 1574 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO))) 1575>; 1576 1577def KIL : Pat < 1578 (int_AMDGPU_kill f32:$src0), 1579 (MASK_WRITE (KILLGT (f32 ZERO), $src0)) 1580>; 1581 1582def : Extract_Element <f32, v4f32, 0, sub0>; 1583def : Extract_Element <f32, v4f32, 1, sub1>; 1584def : Extract_Element <f32, v4f32, 2, sub2>; 1585def : Extract_Element <f32, v4f32, 3, sub3>; 1586 1587def : Insert_Element <f32, v4f32, 0, sub0>; 1588def : Insert_Element <f32, v4f32, 1, sub1>; 1589def : Insert_Element <f32, v4f32, 2, sub2>; 1590def : Insert_Element <f32, v4f32, 3, sub3>; 1591 1592def : Extract_Element <i32, v4i32, 0, sub0>; 1593def : Extract_Element <i32, v4i32, 1, sub1>; 1594def : Extract_Element <i32, v4i32, 2, sub2>; 1595def : Extract_Element <i32, v4i32, 3, sub3>; 1596 1597def : Insert_Element <i32, v4i32, 0, sub0>; 1598def : Insert_Element <i32, v4i32, 1, sub1>; 1599def : Insert_Element <i32, v4i32, 2, sub2>; 1600def : Insert_Element <i32, v4i32, 3, sub3>; 1601 1602def : Extract_Element <f32, v2f32, 0, sub0>; 1603def : Extract_Element <f32, v2f32, 1, sub1>; 1604 1605def : Insert_Element <f32, v2f32, 0, sub0>; 1606def : Insert_Element <f32, v2f32, 1, sub1>; 1607 1608def : Extract_Element <i32, v2i32, 0, sub0>; 1609def : Extract_Element <i32, v2i32, 1, sub1>; 1610 1611def : Insert_Element <i32, v2i32, 0, sub0>; 1612def : Insert_Element <i32, v2i32, 1, sub1>; 1613 1614// bitconvert patterns 1615 1616def : BitConvert <i32, f32, R600_Reg32>; 1617def : BitConvert <f32, i32, R600_Reg32>; 1618def : BitConvert <v2f32, v2i32, R600_Reg64>; 1619def : BitConvert <v2i32, v2f32, R600_Reg64>; 1620def : BitConvert <v4f32, v4i32, R600_Reg128>; 1621def : BitConvert <v4i32, v4f32, R600_Reg128>; 1622 1623// DWORDADDR pattern 1624def : DwordAddrPat <i32, R600_Reg32>; 1625 1626} // End isR600toCayman Predicate 1627 1628def getLDSNoRetOp : InstrMapping { 1629 let FilterClass = "R600_LDS_1A1D"; 1630 let RowFields = ["BaseOp"]; 1631 let ColFields = ["DisableEncoding"]; 1632 let KeyCol = ["$dst"]; 1633 let ValueCols = [[""""]]; 1634} 1635