1//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// R600 has a VLIW architecture.  On pre-cayman cards there are 5 instruction
11// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS.  For cayman cards, the TRANS
12// slot has been removed. 
13//
14//===----------------------------------------------------------------------===//
15
16
17def ALU_X : FuncUnit;
18def ALU_Y : FuncUnit;
19def ALU_Z : FuncUnit;
20def ALU_W : FuncUnit;
21def TRANS : FuncUnit;
22
23def AnyALU : InstrItinClass;
24def VecALU : InstrItinClass;
25def TransALU : InstrItinClass;
26def XALU : InstrItinClass;
27
28def R600_VLIW5_Itin : ProcessorItineraries <
29  [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL],
30  [],
31  [
32    InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
33    InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
34    InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
35    InstrItinData<XALU, [InstrStage<1, [ALU_X]>]>,
36    InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
37  ]
38>;
39
40def R600_VLIW4_Itin : ProcessorItineraries <
41  [ALU_X, ALU_Y, ALU_Z, ALU_W, ALU_NULL],
42  [],
43  [
44    InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
45    InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
46    InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>,
47    InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
48  ]
49>;
50