13492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard//===-- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies --------===// 23492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard// 33492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard// The LLVM Compiler Infrastructure 43492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard// 53492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard// This file is distributed under the University of Illinois Open Source 63492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard// License. See LICENSE.TXT for details. 73492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard// 83492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard//===----------------------------------------------------------------------===// 93492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard// 103492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// \file 113492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// Copies from VGPR to SGPR registers are illegal and the register coalescer 123492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// will sometimes generate these illegal copies in situations like this: 133492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// 143492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// Register Class <vsrc> is the union of <vgpr> and <sgpr> 153492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// 163492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BB0: 173492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg0 <sgpr> = SCALAR_INST 183492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg1 <vsrc> = COPY %vreg0 <sgpr> 193492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// ... 203492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BRANCH %cond BB1, BB2 213492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BB1: 223492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg2 <vgpr> = VECTOR_INST 233492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg3 <vsrc> = COPY %vreg2 <vgpr> 243492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BB2: 253492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1> 26b502e097427e853122d899362ae0a6df3a44e682NAKAMURA Takumi/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc> 27b502e097427e853122d899362ae0a6df3a44e682NAKAMURA Takumi/// 283492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// 293492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// The coalescer will begin at BB0 and eliminate its copy, then the resulting 303492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// code will look like this: 313492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// 323492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BB0: 333492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg0 <sgpr> = SCALAR_INST 343492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// ... 353492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BRANCH %cond BB1, BB2 363492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BB1: 373492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg2 <vgpr> = VECTOR_INST 383492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg3 <vsrc> = COPY %vreg2 <vgpr> 393492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BB2: 403492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <vsrc>, <BB#1> 413492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr> 423492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// 433492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// Now that the result of the PHI instruction is an SGPR, the register 443492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// allocator is now forced to constrain the register class of %vreg3 to 453492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// <sgpr> so we end up with final code like this: 46b502e097427e853122d899362ae0a6df3a44e682NAKAMURA Takumi/// 473492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BB0: 483492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg0 <sgpr> = SCALAR_INST 493492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// ... 503492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BRANCH %cond BB1, BB2 513492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BB1: 523492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg2 <vgpr> = VECTOR_INST 533492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg3 <sgpr> = COPY %vreg2 <vgpr> 543492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// BB2: 553492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1> 563492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr> 573492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// 58b502e097427e853122d899362ae0a6df3a44e682NAKAMURA Takumi/// Now this code contains an illegal copy from a VGPR to an SGPR. 593492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// 603492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// In order to avoid this problem, this pass searches for PHI instructions 613492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// which define a <vsrc> register and constrains its definition class to 623492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// <vgpr> if the user of the PHI's definition register is a vector instruction. 633492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// If the PHI's definition class is constrained to <vgpr> then the coalescer 643492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// will be unable to perform the COPY removal from the above example which 653492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard/// ultimately led to the creation of an illegal COPY. 663492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard//===----------------------------------------------------------------------===// 673492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 683492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard#include "AMDGPU.h" 693492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard#include "SIInstrInfo.h" 703492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard#include "llvm/CodeGen/MachineFunctionPass.h" 71b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard#include "llvm/CodeGen/MachineInstrBuilder.h" 723492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard#include "llvm/CodeGen/MachineRegisterInfo.h" 73b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard#include "llvm/Support/Debug.h" 74ba0e1ee0303d31138c9d94ee5fc52a1c8572876bHans Wennborg#include "llvm/Support/raw_ostream.h" 753492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard#include "llvm/Target/TargetMachine.h" 763492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 773492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellardusing namespace llvm; 783492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 79dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define DEBUG_TYPE "sgpr-copies" 80dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 813492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellardnamespace { 823492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 833492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellardclass SIFixSGPRCopies : public MachineFunctionPass { 843492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 853492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellardprivate: 863492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard static char ID; 87b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI, 883492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard const MachineRegisterInfo &MRI, 89b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned Reg, 90b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned SubReg) const; 91b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI, 92b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const MachineRegisterInfo &MRI, 93b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned Reg, 94b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned SubReg) const; 95b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard bool isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI, 96b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const MachineRegisterInfo &MRI) const; 973492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 983492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellardpublic: 993492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard SIFixSGPRCopies(TargetMachine &tm) : MachineFunctionPass(ID) { } 1003492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 101dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool runOnMachineFunction(MachineFunction &MF) override; 1023492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 103dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const char *getPassName() const override { 1043492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard return "SI Fix SGPR copies"; 1053492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard } 1063492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 1073492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard}; 1083492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 1093492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard} // End anonymous namespace 1103492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 1113492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellardchar SIFixSGPRCopies::ID = 0; 1123492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 1133492eefa4b2509c87598678a6977074a3f6a50e6Tom StellardFunctionPass *llvm::createSIFixSGPRCopiesPass(TargetMachine &tm) { 1143492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard return new SIFixSGPRCopies(tm); 1153492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard} 1163492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 117b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellardstatic bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { 118b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); 119b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 120b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (!MI.getOperand(i).isReg() || 121b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg())) 122b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard continue; 123b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 124b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 125b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return true; 126b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 127b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return false; 128b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard} 129b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 130b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard/// This functions walks the use list of Reg until it finds an Instruction 131b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard/// that isn't a COPY returns the register class of that instruction. 132e59daaa2b83ddb7b6c563e69ef9ae5d67d3a8e07NAKAMURA Takumi/// \return The register defined by the first non-COPY instruction. 133b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellardconst TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses( 134b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const SIRegisterInfo *TRI, 1353492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard const MachineRegisterInfo &MRI, 136b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned Reg, 137b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned SubReg) const { 1383492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard // The Reg parameter to the function must always be defined by either a PHI 1393492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard // or a COPY, therefore it cannot be a physical register. 1403492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard assert(TargetRegisterInfo::isVirtualRegister(Reg) && 1413492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard "Reg cannot be a physical register"); 1423492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 1433492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard const TargetRegisterClass *RC = MRI.getRegClass(Reg); 144b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard RC = TRI->getSubRegClass(RC, SubReg); 14536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineRegisterInfo::use_instr_iterator 14636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) { 1473492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard switch (I->getOpcode()) { 1483492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard case AMDGPU::COPY: 149b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, 150b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard I->getOperand(0).getReg(), 151b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard I->getOperand(0).getSubReg())); 1523492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard break; 1533492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard } 1543492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard } 1553492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 1563492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard return RC; 1573492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard} 1583492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 159b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellardconst TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromDef( 160b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const SIRegisterInfo *TRI, 161b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const MachineRegisterInfo &MRI, 162b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned Reg, 163b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned SubReg) const { 164b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (!TargetRegisterInfo::isVirtualRegister(Reg)) { 165b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); 166b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return TRI->getSubRegClass(RC, SubReg); 167b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 168b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard MachineInstr *Def = MRI.getVRegDef(Reg); 169b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (Def->getOpcode() != AMDGPU::COPY) { 170b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg); 171b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 172b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 173b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(), 174b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard Def->getOperand(1).getSubReg()); 175b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard} 176b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 177b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellardbool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy, 178b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const SIRegisterInfo *TRI, 179b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const MachineRegisterInfo &MRI) const { 180b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 181b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned DstReg = Copy.getOperand(0).getReg(); 182b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned SrcReg = Copy.getOperand(1).getReg(); 183b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned SrcSubReg = Copy.getOperand(1).getSubReg(); 184b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); 185bf9ddd5e8ff207e9b9a1cd484242e8d460f3834eTom Stellard const TargetRegisterClass *SrcRC; 186b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 187b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (!TargetRegisterInfo::isVirtualRegister(SrcReg) || 188dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DstRC == &AMDGPU::M0RegRegClass || 189dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MRI.getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass) 190b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return false; 191b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 19236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg); 193204c953cd59415d7ed50b81c64906bf5a0c97455Tom Stellard return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC); 194b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard} 195b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 1963492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellardbool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { 1973492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard MachineRegisterInfo &MRI = MF.getRegInfo(); 198b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( 199b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard MF.getTarget().getRegisterInfo()); 200b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( 201b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard MF.getTarget().getInstrInfo()); 2023492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 2033492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard BI != BE; ++BI) { 2043492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard 2053492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard MachineBasicBlock &MBB = *BI; 2063492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); 2073492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard I != E; ++I) { 2083492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard MachineInstr &MI = *I; 209b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (MI.getOpcode() == AMDGPU::COPY && isVGPRToSGPRCopy(MI, TRI, MRI)) { 210b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard DEBUG(dbgs() << "Fixing VGPR -> SGPR copy:\n"); 211b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard DEBUG(MI.print(dbgs())); 212b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard TII->moveToVALU(MI); 213b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 214b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 215b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 216b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard switch (MI.getOpcode()) { 217b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard default: continue; 218b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard case AMDGPU::PHI: { 219b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard DEBUG(dbgs() << " Fixing PHI:\n"); 220b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard DEBUG(MI.print(dbgs())); 221b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 222b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard for (unsigned i = 1; i < MI.getNumOperands(); i+=2) { 223b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned Reg = MI.getOperand(i).getReg(); 224b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg, 225b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard MI.getOperand(0).getSubReg()); 226b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard MRI.constrainRegClass(Reg, RC); 227b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 228b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned Reg = MI.getOperand(0).getReg(); 229b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, 230b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard MI.getOperand(0).getSubReg()); 231b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (TRI->getCommonSubClass(RC, &AMDGPU::VReg_32RegClass)) { 232b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass); 233b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 234b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 235b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (!TRI->isSGPRClass(MRI.getRegClass(Reg))) 236b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard break; 237b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 238b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard // If a PHI node defines an SGPR and any of its operands are VGPRs, 239b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard // then we need to move it to the VALU. 240b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard for (unsigned i = 1; i < MI.getNumOperands(); i+=2) { 241b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard unsigned Reg = MI.getOperand(i).getReg(); 242b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (TRI->hasVGPRs(MRI.getRegClass(Reg))) { 243b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard TII->moveToVALU(MI); 244b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard break; 245b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 246b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 247b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 248b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard break; 249b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 250b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard case AMDGPU::REG_SEQUENCE: { 251b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) || 252b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard !hasVGPROperands(MI, TRI)) 253b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard continue; 254b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 255a837ac357cf1354eba301665f643d7e95e26cd51Matt Arsenault DEBUG(dbgs() << "Fixing REG_SEQUENCE:\n"); 256b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard DEBUG(MI.print(dbgs())); 257b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 258b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard TII->moveToVALU(MI); 259b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard break; 2603492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard } 261dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case AMDGPU::INSERT_SUBREG: { 262dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; 263dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DstRC = MRI.getRegClass(MI.getOperand(0).getReg()); 264dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); 265dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Src1RC = MRI.getRegClass(MI.getOperand(2).getReg()); 266dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (TRI->isSGPRClass(DstRC) && 267dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { 268dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n"); 269dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(MI.print(dbgs())); 270dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines TII->moveToVALU(MI); 271dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 272dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines break; 273dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 2743492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard } 2753492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard } 2763492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard } 2773492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard return false; 2783492eefa4b2509c87598678a6977074a3f6a50e6Tom Stellard} 279