SIFixSGPRCopies.cpp revision b502e097427e853122d899362ae0a6df3a44e682 
1//===-- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// Copies from VGPR to SGPR registers are illegal and the register coalescer
12/// will sometimes generate these illegal copies in situations like this:
13///
14///  Register Class <vsrc> is the union of <vgpr> and <sgpr>
15///
16/// BB0:
17///   %vreg0 <sgpr> = SCALAR_INST
18///   %vreg1 <vsrc> = COPY %vreg0 <sgpr>
19///    ...
20///    BRANCH %cond BB1, BB2
21///  BB1:
22///    %vreg2 <vgpr> = VECTOR_INST
23///    %vreg3 <vsrc> = COPY %vreg2 <vgpr>
24///  BB2:
25///    %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1>
26///    %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc>
27///
28///
29/// The coalescer will begin at BB0 and eliminate its copy, then the resulting
30/// code will look like this:
31///
32/// BB0:
33///   %vreg0 <sgpr> = SCALAR_INST
34///    ...
35///    BRANCH %cond BB1, BB2
36/// BB1:
37///   %vreg2 <vgpr> = VECTOR_INST
38///   %vreg3 <vsrc> = COPY %vreg2 <vgpr>
39/// BB2:
40///   %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <vsrc>, <BB#1>
41///   %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
42///
43/// Now that the result of the PHI instruction is an SGPR, the register
44/// allocator is now forced to constrain the register class of %vreg3 to
45/// <sgpr> so we end up with final code like this:
46///
47/// BB0:
48///   %vreg0 <sgpr> = SCALAR_INST
49///    ...
50///    BRANCH %cond BB1, BB2
51/// BB1:
52///   %vreg2 <vgpr> = VECTOR_INST
53///   %vreg3 <sgpr> = COPY %vreg2 <vgpr>
54/// BB2:
55///   %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1>
56///   %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
57///
58/// Now this code contains an illegal copy from a VGPR to an SGPR.
59///
60/// In order to avoid this problem, this pass searches for PHI instructions
61/// which define a <vsrc> register and constrains its definition class to
62/// <vgpr> if the user of the PHI's definition register is a vector instruction.
63/// If the PHI's definition class is constrained to <vgpr> then the coalescer
64/// will be unable to perform the COPY removal from the above example  which
65/// ultimately led to the creation of an illegal COPY.
66//===----------------------------------------------------------------------===//
67
68#define DEBUG_TYPE "sgpr-copies"
69#include "AMDGPU.h"
70#include "SIInstrInfo.h"
71#include "llvm/CodeGen/MachineFunctionPass.h"
72#include "llvm/CodeGen/MachineInstrBuilder.h"
73#include "llvm/CodeGen/MachineRegisterInfo.h"
74#include "llvm/Support/Debug.h"
75#include "llvm/Target/TargetMachine.h"
76
77using namespace llvm;
78
79namespace {
80
81class SIFixSGPRCopies : public MachineFunctionPass {
82
83private:
84  static char ID;
85  const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI,
86                                           const MachineRegisterInfo &MRI,
87                                           unsigned Reg,
88                                           unsigned SubReg) const;
89  const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI,
90                                                 const MachineRegisterInfo &MRI,
91                                                 unsigned Reg,
92                                                 unsigned SubReg) const;
93  bool isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI,
94                        const MachineRegisterInfo &MRI) const;
95
96public:
97  SIFixSGPRCopies(TargetMachine &tm) : MachineFunctionPass(ID) { }
98
99  virtual bool runOnMachineFunction(MachineFunction &MF);
100
101  const char *getPassName() const {
102    return "SI Fix SGPR copies";
103  }
104
105};
106
107} // End anonymous namespace
108
109char SIFixSGPRCopies::ID = 0;
110
111FunctionPass *llvm::createSIFixSGPRCopiesPass(TargetMachine &tm) {
112  return new SIFixSGPRCopies(tm);
113}
114
115static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
116  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
117  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
118    if (!MI.getOperand(i).isReg() ||
119        !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
120      continue;
121
122    if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
123      return true;
124  }
125  return false;
126}
127
128/// This functions walks the use list of Reg until it finds an Instruction
129/// that isn't a COPY returns the register class of that instruction.
130/// \param[out] The register defined by the first non-COPY instruction.
131const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses(
132                                                 const SIRegisterInfo *TRI,
133                                                 const MachineRegisterInfo &MRI,
134                                                 unsigned Reg,
135                                                 unsigned SubReg) const {
136  // The Reg parameter to the function must always be defined by either a PHI
137  // or a COPY, therefore it cannot be a physical register.
138  assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
139         "Reg cannot be a physical register");
140
141  const TargetRegisterClass *RC = MRI.getRegClass(Reg);
142  RC = TRI->getSubRegClass(RC, SubReg);
143  for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg),
144                                         E = MRI.use_end(); I != E; ++I) {
145    switch (I->getOpcode()) {
146    case AMDGPU::COPY:
147      RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
148                                  I->getOperand(0).getReg(),
149                                  I->getOperand(0).getSubReg()));
150      break;
151    }
152  }
153
154  return RC;
155}
156
157const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromDef(
158                                                 const SIRegisterInfo *TRI,
159                                                 const MachineRegisterInfo &MRI,
160                                                 unsigned Reg,
161                                                 unsigned SubReg) const {
162  if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
163    const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg);
164    return TRI->getSubRegClass(RC, SubReg);
165  }
166  MachineInstr *Def = MRI.getVRegDef(Reg);
167  if (Def->getOpcode() != AMDGPU::COPY) {
168    return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg);
169  }
170
171  return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(),
172                                   Def->getOperand(1).getSubReg());
173}
174
175bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy,
176                                      const SIRegisterInfo *TRI,
177                                      const MachineRegisterInfo &MRI) const {
178
179  unsigned DstReg = Copy.getOperand(0).getReg();
180  unsigned SrcReg = Copy.getOperand(1).getReg();
181  unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
182  const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
183
184  if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
185      DstRC == &AMDGPU::M0RegRegClass)
186    return false;
187
188  const TargetRegisterClass *SrcRC = TRI->getSubRegClass(
189      MRI.getRegClass(SrcReg), SrcSubReg);
190
191  return TRI->isSGPRClass(DstRC) &&
192         !TRI->getCommonSubClass(DstRC, SrcRC);
193}
194
195bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
196  MachineRegisterInfo &MRI = MF.getRegInfo();
197  const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
198      MF.getTarget().getRegisterInfo());
199  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
200      MF.getTarget().getInstrInfo());
201  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
202                                                  BI != BE; ++BI) {
203
204    MachineBasicBlock &MBB = *BI;
205    for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
206                                                      I != E; ++I) {
207      MachineInstr &MI = *I;
208      if (MI.getOpcode() == AMDGPU::COPY && isVGPRToSGPRCopy(MI, TRI, MRI)) {
209        DEBUG(dbgs() << "Fixing VGPR -> SGPR copy:\n");
210        DEBUG(MI.print(dbgs()));
211        TII->moveToVALU(MI);
212
213      }
214
215      switch (MI.getOpcode()) {
216      default: continue;
217      case AMDGPU::PHI: {
218        DEBUG(dbgs() << " Fixing PHI:\n");
219        DEBUG(MI.print(dbgs()));
220
221        for (unsigned i = 1; i < MI.getNumOperands(); i+=2) {
222          unsigned Reg = MI.getOperand(i).getReg();
223          const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg,
224                                                  MI.getOperand(0).getSubReg());
225          MRI.constrainRegClass(Reg, RC);
226        }
227        unsigned Reg = MI.getOperand(0).getReg();
228        const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg,
229                                                  MI.getOperand(0).getSubReg());
230        if (TRI->getCommonSubClass(RC, &AMDGPU::VReg_32RegClass)) {
231          MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass);
232        }
233
234        if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
235          break;
236
237        // If a PHI node defines an SGPR and any of its operands are VGPRs,
238        // then we need to move it to the VALU.
239        for (unsigned i = 1; i < MI.getNumOperands(); i+=2) {
240          unsigned Reg = MI.getOperand(i).getReg();
241          if (TRI->hasVGPRs(MRI.getRegClass(Reg))) {
242            TII->moveToVALU(MI);
243            break;
244          }
245        }
246
247        break;
248      }
249      case AMDGPU::REG_SEQUENCE: {
250        if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) ||
251            !hasVGPROperands(MI, TRI))
252          continue;
253
254        DEBUG(dbgs() << "Fixing REG_SEQUENCE: \n");
255        DEBUG(MI.print(dbgs()));
256
257        TII->moveToVALU(MI);
258        TII->legalizeOperands(&MI);
259        break;
260      }
261      }
262    }
263  }
264  return false;
265}
266