SIISelLowering.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Custom DAG lowering for SI
12//
13//===----------------------------------------------------------------------===//
14
15#include "SIISelLowering.h"
16#include "AMDGPU.h"
17#include "AMDGPUSubtarget.h"
18#include "AMDILIntrinsicInfo.h"
19#include "SIInstrInfo.h"
20#include "SIMachineFunctionInfo.h"
21#include "SIRegisterInfo.h"
22#include "llvm/CodeGen/CallingConvLower.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/SelectionDAG.h"
26#include "llvm/IR/Function.h"
27
28using namespace llvm;
29
30SITargetLowering::SITargetLowering(TargetMachine &TM) :
31    AMDGPUTargetLowering(TM) {
32  addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
33  addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
34
35  addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
36  addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
37
38  addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
39  addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
40
41  addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
42  addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
43  addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
44
45  addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
46  addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
47
48  addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
49  addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
50
51  addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
52  addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
53
54  computeRegisterProperties();
55
56  // Condition Codes
57  setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
58  setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
59  setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
60  setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
61  setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
62  setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
63
64  setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
65  setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
66  setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
67  setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
68  setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
69  setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
70
71  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
72  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
73  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
74  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
75
76  setOperationAction(ISD::ADD, MVT::i32, Legal);
77  setOperationAction(ISD::ADDC, MVT::i32, Legal);
78  setOperationAction(ISD::ADDE, MVT::i32, Legal);
79
80  // We need to custom lower vector stores from local memory
81  setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
82  setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
83  setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
84  setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
85
86  setOperationAction(ISD::STORE, MVT::v8i32, Custom);
87  setOperationAction(ISD::STORE, MVT::v16i32, Custom);
88
89  // We need to custom lower loads/stores from private memory
90  setOperationAction(ISD::LOAD, MVT::i32, Custom);
91  setOperationAction(ISD::LOAD, MVT::i64, Custom);
92  setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
93  setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
94  setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
95
96  setOperationAction(ISD::STORE, MVT::i1, Custom);
97  setOperationAction(ISD::STORE, MVT::i32, Custom);
98  setOperationAction(ISD::STORE, MVT::i64, Custom);
99  setOperationAction(ISD::STORE, MVT::v2i32, Custom);
100  setOperationAction(ISD::STORE, MVT::v4i32, Custom);
101
102  setOperationAction(ISD::SELECT, MVT::f32, Promote);
103  AddPromotedToType(ISD::SELECT, MVT::f32, MVT::i32);
104  setOperationAction(ISD::SELECT, MVT::i64, Custom);
105  setOperationAction(ISD::SELECT, MVT::f64, Promote);
106  AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
107
108  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
109  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
110
111  setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
112
113  setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
114  setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
115
116  setOperationAction(ISD::ANY_EXTEND, MVT::i64, Custom);
117  setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
118  setOperationAction(ISD::ZERO_EXTEND, MVT::i64, Custom);
119
120  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
121  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
122  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
123
124  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
125  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
126  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
127
128  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
129  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
130  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
131
132  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
133
134  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
135
136  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
137  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
138  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
139  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
140
141  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
142
143  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
144  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
145  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
146  setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
147  setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
148  setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
149
150  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
151  setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
152  setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
153  setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
154
155  setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
156  setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
157  setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
158  setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
159  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
160
161  setTruncStoreAction(MVT::i32, MVT::i8, Custom);
162  setTruncStoreAction(MVT::i32, MVT::i16, Custom);
163  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
164  setTruncStoreAction(MVT::i64, MVT::i32, Expand);
165  setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
166  setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
167
168  setOperationAction(ISD::LOAD, MVT::i1, Custom);
169
170  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
171  setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
172  setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
173
174  // These should use UDIVREM, so set them to expand
175  setOperationAction(ISD::UDIV, MVT::i64, Expand);
176  setOperationAction(ISD::UREM, MVT::i64, Expand);
177
178  // We only support LOAD/STORE and vector manipulation ops for vectors
179  // with > 4 elements.
180  MVT VecTypes[] = {
181    MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
182  };
183
184  for (MVT VT : VecTypes) {
185    for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
186      switch(Op) {
187      case ISD::LOAD:
188      case ISD::STORE:
189      case ISD::BUILD_VECTOR:
190      case ISD::BITCAST:
191      case ISD::EXTRACT_VECTOR_ELT:
192      case ISD::INSERT_VECTOR_ELT:
193      case ISD::CONCAT_VECTORS:
194      case ISD::INSERT_SUBVECTOR:
195      case ISD::EXTRACT_SUBVECTOR:
196        break;
197      default:
198        setOperationAction(Op, VT, Expand);
199        break;
200      }
201    }
202  }
203
204  for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
205    MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
206    setOperationAction(ISD::FTRUNC, VT, Expand);
207    setOperationAction(ISD::FCEIL, VT, Expand);
208    setOperationAction(ISD::FFLOOR, VT, Expand);
209  }
210
211  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
212    setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
213    setOperationAction(ISD::FCEIL, MVT::f64, Legal);
214    setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
215    setOperationAction(ISD::FRINT, MVT::f64, Legal);
216  }
217
218  setTargetDAGCombine(ISD::SELECT_CC);
219  setTargetDAGCombine(ISD::SETCC);
220
221  setSchedulingPreference(Sched::RegPressure);
222}
223
224//===----------------------------------------------------------------------===//
225// TargetLowering queries
226//===----------------------------------------------------------------------===//
227
228bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT  VT,
229                                                     unsigned AddrSpace,
230                                                     bool *IsFast) const {
231  if (IsFast)
232    *IsFast = false;
233
234  // XXX: This depends on the address space and also we may want to revist
235  // the alignment values we specify in the DataLayout.
236
237  // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
238  // which isn't a simple VT.
239  if (!VT.isSimple() || VT == MVT::Other)
240    return false;
241
242  // XXX - CI changes say "Support for unaligned memory accesses" but I don't
243  // see what for specifically. The wording everywhere else seems to be the
244  // same.
245
246  // 3.6.4 - Operations using pairs of VGPRs (for example: double-floats) have
247  // no alignment restrictions.
248  if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
249    // Using any pair of GPRs should be the same as any other pair.
250    if (IsFast)
251      *IsFast = true;
252    return VT.bitsGE(MVT::i64);
253  }
254
255  // XXX - The only mention I see of this in the ISA manual is for LDS direct
256  // reads the "byte address and must be dword aligned". Is it also true for the
257  // normal loads and stores?
258  if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
259    return false;
260
261  // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
262  // byte-address are ignored, thus forcing Dword alignment.
263  if (IsFast)
264    *IsFast = true;
265  return VT.bitsGT(MVT::i32);
266}
267
268bool SITargetLowering::shouldSplitVectorType(EVT VT) const {
269  return VT.getScalarType().bitsLE(MVT::i16);
270}
271
272bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
273                                                         Type *Ty) const {
274  const SIInstrInfo *TII =
275    static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
276  return TII->isInlineConstant(Imm);
277}
278
279SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
280                                         SDLoc DL, SDValue Chain,
281                                         unsigned Offset, bool Signed) const {
282  MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
283  PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
284                                            AMDGPUAS::CONSTANT_ADDRESS);
285  SDValue BasePtr =  DAG.getCopyFromReg(Chain, DL,
286                           MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
287  SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
288                                             DAG.getConstant(Offset, MVT::i64));
289  return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
290                            MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
291                            false, false, MemVT.getSizeInBits() >> 3);
292
293}
294
295SDValue SITargetLowering::LowerFormalArguments(
296                                      SDValue Chain,
297                                      CallingConv::ID CallConv,
298                                      bool isVarArg,
299                                      const SmallVectorImpl<ISD::InputArg> &Ins,
300                                      SDLoc DL, SelectionDAG &DAG,
301                                      SmallVectorImpl<SDValue> &InVals) const {
302
303  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
304
305  MachineFunction &MF = DAG.getMachineFunction();
306  FunctionType *FType = MF.getFunction()->getFunctionType();
307  SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
308
309  assert(CallConv == CallingConv::C);
310
311  SmallVector<ISD::InputArg, 16> Splits;
312  uint32_t Skipped = 0;
313
314  for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
315    const ISD::InputArg &Arg = Ins[i];
316
317    // First check if it's a PS input addr
318    if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
319        !Arg.Flags.isByVal()) {
320
321      assert((PSInputNum <= 15) && "Too many PS inputs!");
322
323      if (!Arg.Used) {
324        // We can savely skip PS inputs
325        Skipped |= 1 << i;
326        ++PSInputNum;
327        continue;
328      }
329
330      Info->PSInputAddr |= 1 << PSInputNum++;
331    }
332
333    // Second split vertices into their elements
334    if (Info->ShaderType != ShaderType::COMPUTE && Arg.VT.isVector()) {
335      ISD::InputArg NewArg = Arg;
336      NewArg.Flags.setSplit();
337      NewArg.VT = Arg.VT.getVectorElementType();
338
339      // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
340      // three or five element vertex only needs three or five registers,
341      // NOT four or eigth.
342      Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
343      unsigned NumElements = ParamType->getVectorNumElements();
344
345      for (unsigned j = 0; j != NumElements; ++j) {
346        Splits.push_back(NewArg);
347        NewArg.PartOffset += NewArg.VT.getStoreSize();
348      }
349
350    } else if (Info->ShaderType != ShaderType::COMPUTE) {
351      Splits.push_back(Arg);
352    }
353  }
354
355  SmallVector<CCValAssign, 16> ArgLocs;
356  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
357                 getTargetMachine(), ArgLocs, *DAG.getContext());
358
359  // At least one interpolation mode must be enabled or else the GPU will hang.
360  if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) {
361    Info->PSInputAddr |= 1;
362    CCInfo.AllocateReg(AMDGPU::VGPR0);
363    CCInfo.AllocateReg(AMDGPU::VGPR1);
364  }
365
366  // The pointer to the list of arguments is stored in SGPR0, SGPR1
367  if (Info->ShaderType == ShaderType::COMPUTE) {
368    CCInfo.AllocateReg(AMDGPU::SGPR0);
369    CCInfo.AllocateReg(AMDGPU::SGPR1);
370    MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
371  }
372
373  if (Info->ShaderType == ShaderType::COMPUTE) {
374    getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
375                            Splits);
376  }
377
378  AnalyzeFormalArguments(CCInfo, Splits);
379
380  for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
381
382    const ISD::InputArg &Arg = Ins[i];
383    if (Skipped & (1 << i)) {
384      InVals.push_back(DAG.getUNDEF(Arg.VT));
385      continue;
386    }
387
388    CCValAssign &VA = ArgLocs[ArgIdx++];
389    EVT VT = VA.getLocVT();
390
391    if (VA.isMemLoc()) {
392      VT = Ins[i].VT;
393      EVT MemVT = Splits[i].VT;
394      // The first 36 bytes of the input buffer contains information about
395      // thread group and global sizes.
396      SDValue Arg = LowerParameter(DAG, VT, MemVT,  DL, DAG.getRoot(),
397                                   36 + VA.getLocMemOffset(),
398                                   Ins[i].Flags.isSExt());
399      InVals.push_back(Arg);
400      continue;
401    }
402    assert(VA.isRegLoc() && "Parameter must be in a register!");
403
404    unsigned Reg = VA.getLocReg();
405
406    if (VT == MVT::i64) {
407      // For now assume it is a pointer
408      Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
409                                     &AMDGPU::SReg_64RegClass);
410      Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
411      InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
412      continue;
413    }
414
415    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
416
417    Reg = MF.addLiveIn(Reg, RC);
418    SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
419
420    if (Arg.VT.isVector()) {
421
422      // Build a vector from the registers
423      Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
424      unsigned NumElements = ParamType->getVectorNumElements();
425
426      SmallVector<SDValue, 4> Regs;
427      Regs.push_back(Val);
428      for (unsigned j = 1; j != NumElements; ++j) {
429        Reg = ArgLocs[ArgIdx++].getLocReg();
430        Reg = MF.addLiveIn(Reg, RC);
431        Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
432      }
433
434      // Fill up the missing vector elements
435      NumElements = Arg.VT.getVectorNumElements() - NumElements;
436      for (unsigned j = 0; j != NumElements; ++j)
437        Regs.push_back(DAG.getUNDEF(VT));
438
439      InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
440      continue;
441    }
442
443    InVals.push_back(Val);
444  }
445  return Chain;
446}
447
448MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
449    MachineInstr * MI, MachineBasicBlock * BB) const {
450
451  MachineBasicBlock::iterator I = *MI;
452  const SIInstrInfo *TII =
453    static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
454  MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
455
456  switch (MI->getOpcode()) {
457  default:
458    return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
459  case AMDGPU::BRANCH: return BB;
460  case AMDGPU::SI_ADDR64_RSRC: {
461    unsigned SuperReg = MI->getOperand(0).getReg();
462    unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
463    unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
464    unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
465    unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
466    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
467            .addOperand(MI->getOperand(1));
468    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
469            .addImm(0);
470    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
471            .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
472    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
473            .addReg(SubRegHiLo)
474            .addImm(AMDGPU::sub0)
475            .addReg(SubRegHiHi)
476            .addImm(AMDGPU::sub1);
477    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
478            .addReg(SubRegLo)
479            .addImm(AMDGPU::sub0_sub1)
480            .addReg(SubRegHi)
481            .addImm(AMDGPU::sub2_sub3);
482    MI->eraseFromParent();
483    break;
484  }
485  case AMDGPU::V_SUB_F64:
486    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
487            MI->getOperand(0).getReg())
488            .addReg(MI->getOperand(1).getReg())
489            .addReg(MI->getOperand(2).getReg())
490            .addImm(0)  /* src2 */
491            .addImm(0)  /* ABS */
492            .addImm(0)  /* CLAMP */
493            .addImm(0)  /* OMOD */
494            .addImm(2); /* NEG */
495    MI->eraseFromParent();
496    break;
497
498  case AMDGPU::SI_RegisterStorePseudo: {
499    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
500    unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
501    MachineInstrBuilder MIB =
502        BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
503                Reg);
504    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
505      MIB.addOperand(MI->getOperand(i));
506
507    MI->eraseFromParent();
508    break;
509  }
510  case AMDGPU::FABS_SI: {
511    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
512    const SIInstrInfo *TII =
513      static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
514    unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
515    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
516            Reg)
517            .addImm(0x7fffffff);
518    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
519            MI->getOperand(0).getReg())
520            .addReg(MI->getOperand(1).getReg())
521            .addReg(Reg);
522    MI->eraseFromParent();
523    break;
524  }
525  case AMDGPU::FNEG_SI: {
526    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
527    const SIInstrInfo *TII =
528      static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
529    unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
530    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
531            Reg)
532            .addImm(0x80000000);
533    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
534            MI->getOperand(0).getReg())
535            .addReg(MI->getOperand(1).getReg())
536            .addReg(Reg);
537    MI->eraseFromParent();
538    break;
539  }
540  case AMDGPU::FCLAMP_SI: {
541    const SIInstrInfo *TII =
542      static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
543    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
544            MI->getOperand(0).getReg())
545            .addImm(0) // SRC0 modifiers
546            .addOperand(MI->getOperand(1))
547            .addImm(0) // SRC1 modifiers
548            .addImm(0) // SRC1
549            .addImm(1) // CLAMP
550            .addImm(0); // OMOD
551    MI->eraseFromParent();
552  }
553  }
554  return BB;
555}
556
557EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
558  if (!VT.isVector()) {
559    return MVT::i1;
560  }
561  return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
562}
563
564MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
565  return MVT::i32;
566}
567
568bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
569  VT = VT.getScalarType();
570
571  if (!VT.isSimple())
572    return false;
573
574  switch (VT.getSimpleVT().SimpleTy) {
575  case MVT::f32:
576    return false; /* There is V_MAD_F32 for f32 */
577  case MVT::f64:
578    return true;
579  default:
580    break;
581  }
582
583  return false;
584}
585
586//===----------------------------------------------------------------------===//
587// Custom DAG Lowering Operations
588//===----------------------------------------------------------------------===//
589
590SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
591  MachineFunction &MF = DAG.getMachineFunction();
592  SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
593  switch (Op.getOpcode()) {
594  default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
595  case ISD::BRCOND: return LowerBRCOND(Op, DAG);
596  case ISD::LOAD: {
597    LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
598    if (Op.getValueType().isVector() &&
599        (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
600         Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
601         (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
602          Op.getValueType().getVectorNumElements() > 4))) {
603      SDValue MergedValues[2] = {
604        SplitVectorLoad(Op, DAG),
605        Load->getChain()
606      };
607      return DAG.getMergeValues(MergedValues, SDLoc(Op));
608    } else {
609      return LowerLOAD(Op, DAG);
610    }
611  }
612
613  case ISD::SELECT: return LowerSELECT(Op, DAG);
614  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
615  case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
616  case ISD::STORE: return LowerSTORE(Op, DAG);
617  case ISD::ANY_EXTEND: // Fall-through
618  case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
619  case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
620  case ISD::INTRINSIC_WO_CHAIN: {
621    unsigned IntrinsicID =
622                         cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
623    EVT VT = Op.getValueType();
624    SDLoc DL(Op);
625    //XXX: Hardcoded we only use two to store the pointer to the parameters.
626    unsigned NumUserSGPRs = 2;
627    switch (IntrinsicID) {
628    default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
629    case Intrinsic::r600_read_ngroups_x:
630      return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
631    case Intrinsic::r600_read_ngroups_y:
632      return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
633    case Intrinsic::r600_read_ngroups_z:
634      return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
635    case Intrinsic::r600_read_global_size_x:
636      return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
637    case Intrinsic::r600_read_global_size_y:
638      return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
639    case Intrinsic::r600_read_global_size_z:
640      return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
641    case Intrinsic::r600_read_local_size_x:
642      return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
643    case Intrinsic::r600_read_local_size_y:
644      return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
645    case Intrinsic::r600_read_local_size_z:
646      return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
647    case Intrinsic::r600_read_tgid_x:
648      return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
649                     AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 0), VT);
650    case Intrinsic::r600_read_tgid_y:
651      return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
652                     AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 1), VT);
653    case Intrinsic::r600_read_tgid_z:
654      return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
655                     AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 2), VT);
656    case Intrinsic::r600_read_tidig_x:
657      return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
658                                  AMDGPU::VGPR0, VT);
659    case Intrinsic::r600_read_tidig_y:
660      return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
661                                  AMDGPU::VGPR1, VT);
662    case Intrinsic::r600_read_tidig_z:
663      return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
664                                  AMDGPU::VGPR2, VT);
665    case AMDGPUIntrinsic::SI_load_const: {
666      SDValue Ops [] = {
667        Op.getOperand(1),
668        Op.getOperand(2)
669      };
670
671      MachineMemOperand *MMO = MF.getMachineMemOperand(
672          MachinePointerInfo(),
673          MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
674          VT.getSizeInBits() / 8, 4);
675      return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
676                                     Op->getVTList(), Ops, VT, MMO);
677    }
678    case AMDGPUIntrinsic::SI_sample:
679      return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
680    case AMDGPUIntrinsic::SI_sampleb:
681      return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
682    case AMDGPUIntrinsic::SI_sampled:
683      return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
684    case AMDGPUIntrinsic::SI_samplel:
685      return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
686    case AMDGPUIntrinsic::SI_vs_load_input:
687      return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
688                         Op.getOperand(1),
689                         Op.getOperand(2),
690                         Op.getOperand(3));
691    }
692  }
693
694  case ISD::INTRINSIC_VOID:
695    SDValue Chain = Op.getOperand(0);
696    unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
697
698    switch (IntrinsicID) {
699      case AMDGPUIntrinsic::SI_tbuffer_store: {
700        SDLoc DL(Op);
701        SDValue Ops [] = {
702          Chain,
703          Op.getOperand(2),
704          Op.getOperand(3),
705          Op.getOperand(4),
706          Op.getOperand(5),
707          Op.getOperand(6),
708          Op.getOperand(7),
709          Op.getOperand(8),
710          Op.getOperand(9),
711          Op.getOperand(10),
712          Op.getOperand(11),
713          Op.getOperand(12),
714          Op.getOperand(13),
715          Op.getOperand(14)
716        };
717        EVT VT = Op.getOperand(3).getValueType();
718
719        MachineMemOperand *MMO = MF.getMachineMemOperand(
720            MachinePointerInfo(),
721            MachineMemOperand::MOStore,
722            VT.getSizeInBits() / 8, 4);
723        return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
724                                       Op->getVTList(), Ops, VT, MMO);
725      }
726      default:
727        break;
728    }
729  }
730  return SDValue();
731}
732
733/// \brief Helper function for LowerBRCOND
734static SDNode *findUser(SDValue Value, unsigned Opcode) {
735
736  SDNode *Parent = Value.getNode();
737  for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
738       I != E; ++I) {
739
740    if (I.getUse().get() != Value)
741      continue;
742
743    if (I->getOpcode() == Opcode)
744      return *I;
745  }
746  return nullptr;
747}
748
749/// This transforms the control flow intrinsics to get the branch destination as
750/// last parameter, also switches branch target with BR if the need arise
751SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
752                                      SelectionDAG &DAG) const {
753
754  SDLoc DL(BRCOND);
755
756  SDNode *Intr = BRCOND.getOperand(1).getNode();
757  SDValue Target = BRCOND.getOperand(2);
758  SDNode *BR = nullptr;
759
760  if (Intr->getOpcode() == ISD::SETCC) {
761    // As long as we negate the condition everything is fine
762    SDNode *SetCC = Intr;
763    assert(SetCC->getConstantOperandVal(1) == 1);
764    assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
765           ISD::SETNE);
766    Intr = SetCC->getOperand(0).getNode();
767
768  } else {
769    // Get the target from BR if we don't negate the condition
770    BR = findUser(BRCOND, ISD::BR);
771    Target = BR->getOperand(1);
772  }
773
774  assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
775
776  // Build the result and
777  SmallVector<EVT, 4> Res;
778  for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
779    Res.push_back(Intr->getValueType(i));
780
781  // operands of the new intrinsic call
782  SmallVector<SDValue, 4> Ops;
783  Ops.push_back(BRCOND.getOperand(0));
784  for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
785    Ops.push_back(Intr->getOperand(i));
786  Ops.push_back(Target);
787
788  // build the new intrinsic call
789  SDNode *Result = DAG.getNode(
790    Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
791    DAG.getVTList(Res), Ops).getNode();
792
793  if (BR) {
794    // Give the branch instruction our target
795    SDValue Ops[] = {
796      BR->getOperand(0),
797      BRCOND.getOperand(2)
798    };
799    DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops);
800  }
801
802  SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
803
804  // Copy the intrinsic results to registers
805  for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
806    SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
807    if (!CopyToReg)
808      continue;
809
810    Chain = DAG.getCopyToReg(
811      Chain, DL,
812      CopyToReg->getOperand(1),
813      SDValue(Result, i - 1),
814      SDValue());
815
816    DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
817  }
818
819  // Remove the old intrinsic from the chain
820  DAG.ReplaceAllUsesOfValueWith(
821    SDValue(Intr, Intr->getNumValues() - 1),
822    Intr->getOperand(0));
823
824  return Chain;
825}
826
827SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
828  SDLoc DL(Op);
829  LoadSDNode *Load = cast<LoadSDNode>(Op);
830  SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
831  SDValue MergedValues[2];
832  MergedValues[1] = Load->getChain();
833  if (Ret.getNode()) {
834    MergedValues[0] = Ret;
835    return DAG.getMergeValues(MergedValues, DL);
836  }
837
838  if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
839    return SDValue();
840  }
841
842  EVT MemVT = Load->getMemoryVT();
843
844  assert(!MemVT.isVector() && "Private loads should be scalarized");
845  assert(!MemVT.isFloatingPoint() && "FP loads should be promoted to int");
846
847  SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
848                            DAG.getConstant(2, MVT::i32));
849  Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
850                    Load->getChain(), Ptr,
851                    DAG.getTargetConstant(0, MVT::i32),
852                    Op.getOperand(2));
853  if (MemVT.getSizeInBits() == 64) {
854    SDValue IncPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
855                                 DAG.getConstant(1, MVT::i32));
856
857    SDValue LoadUpper = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
858                                    Load->getChain(), IncPtr,
859                                    DAG.getTargetConstant(0, MVT::i32),
860                                    Op.getOperand(2));
861
862    Ret = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ret, LoadUpper);
863  }
864
865  MergedValues[0] = Ret;
866  return DAG.getMergeValues(MergedValues, DL);
867
868}
869
870SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
871                                               const SDValue &Op,
872                                               SelectionDAG &DAG) const {
873  return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
874                     Op.getOperand(2),
875                     Op.getOperand(3),
876                     Op.getOperand(4));
877}
878
879SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
880  if (Op.getValueType() != MVT::i64)
881    return SDValue();
882
883  SDLoc DL(Op);
884  SDValue Cond = Op.getOperand(0);
885
886  SDValue Zero = DAG.getConstant(0, MVT::i32);
887  SDValue One = DAG.getConstant(1, MVT::i32);
888
889  SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
890  SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
891
892  SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
893  SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
894
895  SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
896
897  SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
898  SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
899
900  SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
901
902  SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
903  return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
904}
905
906SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
907  SDValue LHS = Op.getOperand(0);
908  SDValue RHS = Op.getOperand(1);
909  SDValue True = Op.getOperand(2);
910  SDValue False = Op.getOperand(3);
911  SDValue CC = Op.getOperand(4);
912  EVT VT = Op.getValueType();
913  SDLoc DL(Op);
914
915  SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
916  return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
917}
918
919SDValue SITargetLowering::LowerSIGN_EXTEND(SDValue Op,
920                                           SelectionDAG &DAG) const {
921  EVT VT = Op.getValueType();
922  SDLoc DL(Op);
923
924  if (VT != MVT::i64) {
925    return SDValue();
926  }
927
928  SDValue Hi = DAG.getNode(ISD::SRA, DL, MVT::i32, Op.getOperand(0),
929                                                 DAG.getConstant(31, MVT::i32));
930
931  return DAG.getNode(ISD::BUILD_PAIR, DL, VT, Op.getOperand(0), Hi);
932}
933
934SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
935  SDLoc DL(Op);
936  StoreSDNode *Store = cast<StoreSDNode>(Op);
937  EVT VT = Store->getMemoryVT();
938
939  SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
940  if (Ret.getNode())
941    return Ret;
942
943  if (VT.isVector() && VT.getVectorNumElements() >= 8)
944      return SplitVectorStore(Op, DAG);
945
946  if (VT == MVT::i1)
947    return DAG.getTruncStore(Store->getChain(), DL,
948                        DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
949                        Store->getBasePtr(), MVT::i1, Store->getMemOperand());
950
951  if (Store->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
952    return SDValue();
953
954  SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Store->getBasePtr(),
955                            DAG.getConstant(2, MVT::i32));
956  SDValue Chain = Store->getChain();
957  SmallVector<SDValue, 8> Values;
958
959  if (Store->isTruncatingStore()) {
960    unsigned Mask = 0;
961    if (Store->getMemoryVT() == MVT::i8) {
962      Mask = 0xff;
963    } else if (Store->getMemoryVT() == MVT::i16) {
964      Mask = 0xffff;
965    }
966    SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
967                              Chain, Store->getBasePtr(),
968                              DAG.getConstant(0, MVT::i32));
969    SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getBasePtr(),
970                                  DAG.getConstant(0x3, MVT::i32));
971    SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
972                                   DAG.getConstant(3, MVT::i32));
973    SDValue MaskedValue = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getValue(),
974                                      DAG.getConstant(Mask, MVT::i32));
975    SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
976                                       MaskedValue, ShiftAmt);
977    SDValue RotrAmt = DAG.getNode(ISD::SUB, DL, MVT::i32,
978                                  DAG.getConstant(32, MVT::i32), ShiftAmt);
979    SDValue DstMask = DAG.getNode(ISD::ROTR, DL, MVT::i32,
980                                  DAG.getConstant(Mask, MVT::i32),
981                                  RotrAmt);
982    Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
983    Dst = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
984
985    Values.push_back(Dst);
986  } else if (VT == MVT::i64) {
987    for (unsigned i = 0; i < 2; ++i) {
988      Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
989                       Store->getValue(), DAG.getConstant(i, MVT::i32)));
990    }
991  } else if (VT == MVT::i128) {
992    for (unsigned i = 0; i < 2; ++i) {
993      for (unsigned j = 0; j < 2; ++j) {
994        Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
995                           DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64,
996                           Store->getValue(), DAG.getConstant(i, MVT::i32)),
997                         DAG.getConstant(j, MVT::i32)));
998      }
999    }
1000  } else {
1001    Values.push_back(Store->getValue());
1002  }
1003
1004  for (unsigned i = 0; i < Values.size(); ++i) {
1005    SDValue PartPtr = DAG.getNode(ISD::ADD, DL, MVT::i32,
1006                                  Ptr, DAG.getConstant(i, MVT::i32));
1007    Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1008                        Chain, Values[i], PartPtr,
1009                        DAG.getTargetConstant(0, MVT::i32));
1010  }
1011  return Chain;
1012}
1013
1014
1015SDValue SITargetLowering::LowerZERO_EXTEND(SDValue Op,
1016                                           SelectionDAG &DAG) const {
1017  EVT VT = Op.getValueType();
1018  SDLoc DL(Op);
1019
1020  if (VT != MVT::i64) {
1021    return SDValue();
1022  }
1023
1024  SDValue Src = Op.getOperand(0);
1025  if (Src.getValueType() != MVT::i32)
1026    Src = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Src);
1027
1028  SDValue Zero = DAG.getConstant(0, MVT::i32);
1029  return DAG.getNode(ISD::BUILD_PAIR, DL, VT, Src, Zero);
1030}
1031
1032//===----------------------------------------------------------------------===//
1033// Custom DAG optimizations
1034//===----------------------------------------------------------------------===//
1035
1036SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1037                                            DAGCombinerInfo &DCI) const {
1038  SelectionDAG &DAG = DCI.DAG;
1039  SDLoc DL(N);
1040  EVT VT = N->getValueType(0);
1041
1042  switch (N->getOpcode()) {
1043    default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1044    case ISD::SELECT_CC: {
1045      ConstantSDNode *True, *False;
1046      // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
1047      if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1048          && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1049          && True->isAllOnesValue()
1050          && False->isNullValue()
1051          && VT == MVT::i1) {
1052        return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
1053                           N->getOperand(1), N->getOperand(4));
1054
1055      }
1056      break;
1057    }
1058    case ISD::SETCC: {
1059      SDValue Arg0 = N->getOperand(0);
1060      SDValue Arg1 = N->getOperand(1);
1061      SDValue CC = N->getOperand(2);
1062      ConstantSDNode * C = nullptr;
1063      ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1064
1065      // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1066      if (VT == MVT::i1
1067          && Arg0.getOpcode() == ISD::SIGN_EXTEND
1068          && Arg0.getOperand(0).getValueType() == MVT::i1
1069          && (C = dyn_cast<ConstantSDNode>(Arg1))
1070          && C->isNullValue()
1071          && CCOp == ISD::SETNE) {
1072        return SimplifySetCC(VT, Arg0.getOperand(0),
1073                             DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1074      }
1075      break;
1076    }
1077  }
1078
1079  return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1080}
1081
1082/// \brief Test if RegClass is one of the VSrc classes
1083static bool isVSrc(unsigned RegClass) {
1084  return AMDGPU::VSrc_32RegClassID == RegClass ||
1085         AMDGPU::VSrc_64RegClassID == RegClass;
1086}
1087
1088/// \brief Test if RegClass is one of the SSrc classes
1089static bool isSSrc(unsigned RegClass) {
1090  return AMDGPU::SSrc_32RegClassID == RegClass ||
1091         AMDGPU::SSrc_64RegClassID == RegClass;
1092}
1093
1094/// \brief Analyze the possible immediate value Op
1095///
1096/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1097/// and the immediate value if it's a literal immediate
1098int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1099
1100  union {
1101    int32_t I;
1102    float F;
1103  } Imm;
1104
1105  if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1106    if (Node->getZExtValue() >> 32) {
1107        return -1;
1108    }
1109    Imm.I = Node->getSExtValue();
1110  } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1111    if (N->getValueType(0) != MVT::f32)
1112      return -1;
1113    Imm.F = Node->getValueAPF().convertToFloat();
1114  } else
1115    return -1; // It isn't an immediate
1116
1117  if ((Imm.I >= -16 && Imm.I <= 64) ||
1118      Imm.F == 0.5f || Imm.F == -0.5f ||
1119      Imm.F == 1.0f || Imm.F == -1.0f ||
1120      Imm.F == 2.0f || Imm.F == -2.0f ||
1121      Imm.F == 4.0f || Imm.F == -4.0f)
1122    return 0; // It's an inline immediate
1123
1124  return Imm.I; // It's a literal immediate
1125}
1126
1127/// \brief Try to fold an immediate directly into an instruction
1128bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1129                               bool &ScalarSlotUsed) const {
1130
1131  MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1132  const SIInstrInfo *TII =
1133    static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1134  if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1135    return false;
1136
1137  const SDValue &Op = Mov->getOperand(0);
1138  int32_t Value = analyzeImmediate(Op.getNode());
1139  if (Value == -1) {
1140    // Not an immediate at all
1141    return false;
1142
1143  } else if (Value == 0) {
1144    // Inline immediates can always be fold
1145    Operand = Op;
1146    return true;
1147
1148  } else if (Value == Immediate) {
1149    // Already fold literal immediate
1150    Operand = Op;
1151    return true;
1152
1153  } else if (!ScalarSlotUsed && !Immediate) {
1154    // Fold this literal immediate
1155    ScalarSlotUsed = true;
1156    Immediate = Value;
1157    Operand = Op;
1158    return true;
1159
1160  }
1161
1162  return false;
1163}
1164
1165const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1166                                   SelectionDAG &DAG, const SDValue &Op) const {
1167  const SIInstrInfo *TII =
1168    static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1169  const SIRegisterInfo &TRI = TII->getRegisterInfo();
1170
1171  if (!Op->isMachineOpcode()) {
1172    switch(Op->getOpcode()) {
1173    case ISD::CopyFromReg: {
1174      MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1175      unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1176      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1177        return MRI.getRegClass(Reg);
1178      }
1179      return TRI.getPhysRegClass(Reg);
1180    }
1181    default:  return nullptr;
1182    }
1183  }
1184  const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1185  int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1186  if (OpClassID != -1) {
1187    return TRI.getRegClass(OpClassID);
1188  }
1189  switch(Op.getMachineOpcode()) {
1190  case AMDGPU::COPY_TO_REGCLASS:
1191    // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1192    OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1193
1194    // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1195    // class, then the register class for the value could be either a
1196    // VReg or and SReg.  In order to get a more accurate
1197    if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1198        OpClassID == AMDGPU::VSrc_64RegClassID) {
1199      return getRegClassForNode(DAG, Op.getOperand(0));
1200    }
1201    return TRI.getRegClass(OpClassID);
1202  case AMDGPU::EXTRACT_SUBREG: {
1203    int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1204    const TargetRegisterClass *SuperClass =
1205      getRegClassForNode(DAG, Op.getOperand(0));
1206    return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1207  }
1208  case AMDGPU::REG_SEQUENCE:
1209    // Operand 0 is the register class id for REG_SEQUENCE instructions.
1210    return TRI.getRegClass(
1211      cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1212  default:
1213    return getRegClassFor(Op.getSimpleValueType());
1214  }
1215}
1216
1217/// \brief Does "Op" fit into register class "RegClass" ?
1218bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1219                                    unsigned RegClass) const {
1220  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1221  const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1222  if (!RC) {
1223    return false;
1224  }
1225  return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1226}
1227
1228/// \brief Make sure that we don't exeed the number of allowed scalars
1229void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
1230                                       unsigned RegClass,
1231                                       bool &ScalarSlotUsed) const {
1232
1233  // First map the operands register class to a destination class
1234  if (RegClass == AMDGPU::VSrc_32RegClassID)
1235    RegClass = AMDGPU::VReg_32RegClassID;
1236  else if (RegClass == AMDGPU::VSrc_64RegClassID)
1237    RegClass = AMDGPU::VReg_64RegClassID;
1238  else
1239    return;
1240
1241  // Nothing to do if they fit naturally
1242  if (fitsRegClass(DAG, Operand, RegClass))
1243    return;
1244
1245  // If the scalar slot isn't used yet use it now
1246  if (!ScalarSlotUsed) {
1247    ScalarSlotUsed = true;
1248    return;
1249  }
1250
1251  // This is a conservative aproach. It is possible that we can't determine the
1252  // correct register class and copy too often, but better safe than sorry.
1253  SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1254  SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
1255                                    Operand.getValueType(), Operand, RC);
1256  Operand = SDValue(Node, 0);
1257}
1258
1259/// \returns true if \p Node's operands are different from the SDValue list
1260/// \p Ops
1261static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1262  for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1263    if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1264      return true;
1265    }
1266  }
1267  return false;
1268}
1269
1270/// \brief Try to fold the Nodes operands into the Node
1271SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
1272                                       SelectionDAG &DAG) const {
1273
1274  // Original encoding (either e32 or e64)
1275  int Opcode = Node->getMachineOpcode();
1276  const SIInstrInfo *TII =
1277    static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1278  const MCInstrDesc *Desc = &TII->get(Opcode);
1279
1280  unsigned NumDefs = Desc->getNumDefs();
1281  unsigned NumOps = Desc->getNumOperands();
1282
1283  // Commuted opcode if available
1284  int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1285  const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1286
1287  assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1288  assert(!DescRev || DescRev->getNumOperands() == NumOps);
1289
1290  // e64 version if available, -1 otherwise
1291  int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1292  const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
1293  int InputModifiers[3] = {0};
1294
1295  assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
1296
1297  int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1298  bool HaveVSrc = false, HaveSSrc = false;
1299
1300  // First figure out what we alread have in this instruction
1301  for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1302       i != e && Op < NumOps; ++i, ++Op) {
1303
1304    unsigned RegClass = Desc->OpInfo[Op].RegClass;
1305    if (isVSrc(RegClass))
1306      HaveVSrc = true;
1307    else if (isSSrc(RegClass))
1308      HaveSSrc = true;
1309    else
1310      continue;
1311
1312    int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1313    if (Imm != -1 && Imm != 0) {
1314      // Literal immediate
1315      Immediate = Imm;
1316    }
1317  }
1318
1319  // If we neither have VSrc nor SSrc it makes no sense to continue
1320  if (!HaveVSrc && !HaveSSrc)
1321    return Node;
1322
1323  // No scalar allowed when we have both VSrc and SSrc
1324  bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1325
1326  // Second go over the operands and try to fold them
1327  std::vector<SDValue> Ops;
1328  bool Promote2e64 = false;
1329  for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1330       i != e && Op < NumOps; ++i, ++Op) {
1331
1332    const SDValue &Operand = Node->getOperand(i);
1333    Ops.push_back(Operand);
1334
1335    // Already folded immediate ?
1336    if (isa<ConstantSDNode>(Operand.getNode()) ||
1337        isa<ConstantFPSDNode>(Operand.getNode()))
1338      continue;
1339
1340    // Is this a VSrc or SSrc operand ?
1341    unsigned RegClass = Desc->OpInfo[Op].RegClass;
1342    if (isVSrc(RegClass) || isSSrc(RegClass)) {
1343      // Try to fold the immediates
1344      if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
1345        // Folding didn't worked, make sure we don't hit the SReg limit
1346        ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1347      }
1348      continue;
1349    }
1350
1351    if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1352
1353      unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1354      assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1355
1356      // Test if it makes sense to swap operands
1357      if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1358          (!fitsRegClass(DAG, Ops[1], RegClass) &&
1359           fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1360
1361        // Swap commutable operands
1362        std::swap(Ops[0], Ops[1]);
1363
1364        Desc = DescRev;
1365        DescRev = nullptr;
1366        continue;
1367      }
1368    }
1369
1370    if (Immediate)
1371      continue;
1372
1373    if (DescE64) {
1374
1375      // Test if it makes sense to switch to e64 encoding
1376      unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1377      if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
1378        continue;
1379
1380      int32_t TmpImm = -1;
1381      if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
1382          (!fitsRegClass(DAG, Ops[i], RegClass) &&
1383           fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1384
1385        // Switch to e64 encoding
1386        Immediate = -1;
1387        Promote2e64 = true;
1388        Desc = DescE64;
1389        DescE64 = nullptr;
1390      }
1391    }
1392
1393    if (!DescE64 && !Promote2e64)
1394      continue;
1395    if (!Operand.isMachineOpcode())
1396      continue;
1397    if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) {
1398      Ops.pop_back();
1399      Ops.push_back(Operand.getOperand(0));
1400      InputModifiers[i] = 1;
1401      Promote2e64 = true;
1402      if (!DescE64)
1403        continue;
1404      Desc = DescE64;
1405      DescE64 = 0;
1406    }
1407    else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) {
1408      Ops.pop_back();
1409      Ops.push_back(Operand.getOperand(0));
1410      InputModifiers[i] = 2;
1411      Promote2e64 = true;
1412      if (!DescE64)
1413        continue;
1414      Desc = DescE64;
1415      DescE64 = 0;
1416    }
1417  }
1418
1419  if (Promote2e64) {
1420    std::vector<SDValue> OldOps(Ops);
1421    Ops.clear();
1422    for (unsigned i = 0; i < OldOps.size(); ++i) {
1423      // src_modifier
1424      Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
1425      Ops.push_back(OldOps[i]);
1426    }
1427    // Add the modifier flags while promoting
1428    for (unsigned i = 0; i < 2; ++i)
1429      Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
1430  }
1431
1432  // Add optional chain and glue
1433  for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1434    Ops.push_back(Node->getOperand(i));
1435
1436  // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1437  // this case a brand new node is always be created, even if the operands
1438  // are the same as before.  So, manually check if anything has been changed.
1439  if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1440    return Node;
1441  }
1442
1443  // Create a complete new instruction
1444  return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1445}
1446
1447/// \brief Helper function for adjustWritemask
1448static unsigned SubIdx2Lane(unsigned Idx) {
1449  switch (Idx) {
1450  default: return 0;
1451  case AMDGPU::sub0: return 0;
1452  case AMDGPU::sub1: return 1;
1453  case AMDGPU::sub2: return 2;
1454  case AMDGPU::sub3: return 3;
1455  }
1456}
1457
1458/// \brief Adjust the writemask of MIMG instructions
1459void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1460                                       SelectionDAG &DAG) const {
1461  SDNode *Users[4] = { };
1462  unsigned Lane = 0;
1463  unsigned OldDmask = Node->getConstantOperandVal(0);
1464  unsigned NewDmask = 0;
1465
1466  // Try to figure out the used register components
1467  for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1468       I != E; ++I) {
1469
1470    // Abort if we can't understand the usage
1471    if (!I->isMachineOpcode() ||
1472        I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1473      return;
1474
1475    // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1476    // Note that subregs are packed, i.e. Lane==0 is the first bit set
1477    // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1478    // set, etc.
1479    Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1480
1481    // Set which texture component corresponds to the lane.
1482    unsigned Comp;
1483    for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1484      assert(Dmask);
1485      Comp = countTrailingZeros(Dmask);
1486      Dmask &= ~(1 << Comp);
1487    }
1488
1489    // Abort if we have more than one user per component
1490    if (Users[Lane])
1491      return;
1492
1493    Users[Lane] = *I;
1494    NewDmask |= 1 << Comp;
1495  }
1496
1497  // Abort if there's no change
1498  if (NewDmask == OldDmask)
1499    return;
1500
1501  // Adjust the writemask in the node
1502  std::vector<SDValue> Ops;
1503  Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1504  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1505    Ops.push_back(Node->getOperand(i));
1506  Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1507
1508  // If we only got one lane, replace it with a copy
1509  // (if NewDmask has only one bit set...)
1510  if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1511    SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1512    SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1513                                      SDLoc(), Users[Lane]->getValueType(0),
1514                                      SDValue(Node, 0), RC);
1515    DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1516    return;
1517  }
1518
1519  // Update the users of the node with the new indices
1520  for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1521
1522    SDNode *User = Users[i];
1523    if (!User)
1524      continue;
1525
1526    SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1527    DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1528
1529    switch (Idx) {
1530    default: break;
1531    case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1532    case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1533    case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1534    }
1535  }
1536}
1537
1538/// \brief Fold the instructions after slecting them
1539SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1540                                          SelectionDAG &DAG) const {
1541  const SIInstrInfo *TII =
1542      static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1543  Node = AdjustRegClass(Node, DAG);
1544
1545  if (TII->isMIMG(Node->getMachineOpcode()))
1546    adjustWritemask(Node, DAG);
1547
1548  return foldOperands(Node, DAG);
1549}
1550
1551/// \brief Assign the register class depending on the number of
1552/// bits set in the writemask
1553void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1554                                                     SDNode *Node) const {
1555  const SIInstrInfo *TII =
1556      static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1557  if (!TII->isMIMG(MI->getOpcode()))
1558    return;
1559
1560  unsigned VReg = MI->getOperand(0).getReg();
1561  unsigned Writemask = MI->getOperand(1).getImm();
1562  unsigned BitsSet = 0;
1563  for (unsigned i = 0; i < 4; ++i)
1564    BitsSet += Writemask & (1 << i) ? 1 : 0;
1565
1566  const TargetRegisterClass *RC;
1567  switch (BitsSet) {
1568  default: return;
1569  case 1:  RC = &AMDGPU::VReg_32RegClass; break;
1570  case 2:  RC = &AMDGPU::VReg_64RegClass; break;
1571  case 3:  RC = &AMDGPU::VReg_96RegClass; break;
1572  }
1573
1574  unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1575  MI->setDesc(TII->get(NewOpcode));
1576  MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1577  MRI.setRegClass(VReg, RC);
1578}
1579
1580MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1581                                                SelectionDAG &DAG) const {
1582
1583  SDLoc DL(N);
1584  unsigned NewOpcode = N->getMachineOpcode();
1585
1586  switch (N->getMachineOpcode()) {
1587  default: return N;
1588  case AMDGPU::S_LOAD_DWORD_IMM:
1589    NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1590    // Fall-through
1591  case AMDGPU::S_LOAD_DWORDX2_SGPR:
1592    if (NewOpcode == N->getMachineOpcode()) {
1593      NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1594    }
1595    // Fall-through
1596  case AMDGPU::S_LOAD_DWORDX4_IMM:
1597  case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1598    if (NewOpcode == N->getMachineOpcode()) {
1599      NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1600    }
1601    if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1602      return N;
1603    }
1604    ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
1605    SDValue Ops[] = {
1606      SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
1607                                 DAG.getConstant(0, MVT::i64)), 0),
1608      N->getOperand(0),
1609      DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
1610    };
1611    return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
1612  }
1613  }
1614}
1615
1616SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1617                                               const TargetRegisterClass *RC,
1618                                               unsigned Reg, EVT VT) const {
1619  SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1620
1621  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1622                            cast<RegisterSDNode>(VReg)->getReg(), VT);
1623}
1624