SIISelLowering.h revision a2b4eb6d15a13de257319ac6231b5ab622cd02b1 
1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief SI DAG Lowering interface definition
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SIISELLOWERING_H
16#define SIISELLOWERING_H
17
18#include "AMDGPUISelLowering.h"
19#include "SIInstrInfo.h"
20
21namespace llvm {
22
23class SITargetLowering : public AMDGPUTargetLowering {
24  SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25                         SDValue Chain, unsigned Offset) const;
26  SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27                               SelectionDAG &DAG) const;
28  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
29  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
30  SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
31  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
32  SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
33  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
34
35  SDValue ResourceDescriptorToi128(SDValue Op, SelectionDAG &DAG) const;
36  bool foldImm(SDValue &Operand, int32_t &Immediate,
37               bool &ScalarSlotUsed) const;
38  const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
39                                                const SDValue &Op) const;
40  bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
41                    unsigned RegClass) const;
42  void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
43                       unsigned RegClass, bool &ScalarSlotUsed) const;
44
45  SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
46  void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
47  MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
48
49public:
50  SITargetLowering(TargetMachine &tm);
51  bool allowsUnalignedMemoryAccesses(EVT  VT, bool *IsFast) const;
52  virtual bool shouldSplitVectorElementType(EVT VT) const;
53
54  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
55                               bool isVarArg,
56                               const SmallVectorImpl<ISD::InputArg> &Ins,
57                               SDLoc DL, SelectionDAG &DAG,
58                               SmallVectorImpl<SDValue> &InVals) const;
59
60  virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
61                                              MachineBasicBlock * BB) const;
62  virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
63  virtual MVT getScalarShiftAmountTy(EVT VT) const;
64  virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
65  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
66  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
67  virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
68  virtual void AdjustInstrPostInstrSelection(MachineInstr *MI,
69                                             SDNode *Node) const;
70
71  int32_t analyzeImmediate(const SDNode *N) const;
72  SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
73                               unsigned Reg, EVT VT) const;
74};
75
76} // End namespace llvm
77
78#endif //SIISELLOWERING_H
79