SIISelLowering.h revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb
1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10/// \file 11/// \brief SI DAG Lowering interface definition 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef SIISELLOWERING_H 16#define SIISELLOWERING_H 17 18#include "AMDGPUISelLowering.h" 19#include "SIInstrInfo.h" 20 21namespace llvm { 22 23class SITargetLowering : public AMDGPUTargetLowering { 24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL, 25 SDValue Chain, unsigned Offset, bool Signed) const; 26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op, 27 SelectionDAG &DAG) const; 28 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 29 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 30 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 31 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 32 33 bool foldImm(SDValue &Operand, int32_t &Immediate, 34 bool &ScalarSlotUsed) const; 35 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG, 36 const SDValue &Op) const; 37 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op, 38 unsigned RegClass) const; 39 void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand, 40 unsigned RegClass, bool &ScalarSlotUsed) const; 41 42 SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const; 43 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 44 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const; 45 46 static SDValue performUCharToFloatCombine(SDNode *N, 47 DAGCombinerInfo &DCI); 48 49public: 50 SITargetLowering(TargetMachine &tm); 51 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS, 52 bool *IsFast) const override; 53 54 TargetLoweringBase::LegalizeTypeAction 55 getPreferredVectorAction(EVT VT) const override; 56 57 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 58 Type *Ty) const override; 59 60 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 61 bool isVarArg, 62 const SmallVectorImpl<ISD::InputArg> &Ins, 63 SDLoc DL, SelectionDAG &DAG, 64 SmallVectorImpl<SDValue> &InVals) const override; 65 66 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI, 67 MachineBasicBlock * BB) const override; 68 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 69 MVT getScalarShiftAmountTy(EVT VT) const override; 70 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 71 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 72 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 73 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 74 void AdjustInstrPostInstrSelection(MachineInstr *MI, 75 SDNode *Node) const override; 76 77 int32_t analyzeImmediate(const SDNode *N) const; 78 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 79 unsigned Reg, EVT VT) const override; 80}; 81 82} // End namespace llvm 83 84#endif //SIISELLOWERING_H 85