1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15    AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
16
17  field bits<1> VM_CNT = 0;
18  field bits<1> EXP_CNT = 0;
19  field bits<1> LGKM_CNT = 0;
20  field bits<1> MIMG = 0;
21  field bits<1> SMRD = 0;
22  field bits<1> VOP1 = 0;
23  field bits<1> VOP2 = 0;
24  field bits<1> VOP3 = 0;
25  field bits<1> VOPC = 0;
26  field bits<1> SALU = 0;
27
28  let TSFlags{0} = VM_CNT;
29  let TSFlags{1} = EXP_CNT;
30  let TSFlags{2} = LGKM_CNT;
31  let TSFlags{3} = MIMG;
32  let TSFlags{4} = SMRD;
33  let TSFlags{5} = VOP1;
34  let TSFlags{6} = VOP2;
35  let TSFlags{7} = VOP3;
36  let TSFlags{8} = VOPC;
37  let TSFlags{9} = SALU;
38}
39
40class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
41    InstSI <outs, ins, asm, pattern> {
42
43  field bits<32> Inst;
44  let Size = 4;
45}
46
47class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
48    InstSI <outs, ins, asm, pattern> {
49
50  field bits<64> Inst;
51  let Size = 8;
52}
53
54class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
55    Enc64 <outs, ins, asm, pattern> {
56
57  let mayLoad = 0;
58  let mayStore = 0;
59  let hasSideEffects = 0;
60  let UseNamedOperandTable = 1;
61  let VOP3 = 1;
62}
63
64//===----------------------------------------------------------------------===//
65// Scalar operations
66//===----------------------------------------------------------------------===//
67
68class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
69    Enc32<outs, ins, asm, pattern> {
70
71  bits<7> SDST;
72  bits<8> SSRC0;
73
74  let Inst{7-0} = SSRC0;
75  let Inst{15-8} = op;
76  let Inst{22-16} = SDST;
77  let Inst{31-23} = 0x17d; //encoding;
78
79  let mayLoad = 0;
80  let mayStore = 0;
81  let hasSideEffects = 0;
82  let SALU = 1;
83}
84
85class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
86    Enc32 <outs, ins, asm, pattern> {
87  
88  bits<7> SDST;
89  bits<8> SSRC0;
90  bits<8> SSRC1;
91
92  let Inst{7-0} = SSRC0;
93  let Inst{15-8} = SSRC1;
94  let Inst{22-16} = SDST;
95  let Inst{29-23} = op;
96  let Inst{31-30} = 0x2; // encoding
97
98  let mayLoad = 0;
99  let mayStore = 0;
100  let hasSideEffects = 0;
101  let SALU = 1;
102}
103
104class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
105  Enc32<outs, ins, asm, pattern> {
106
107  bits<8> SSRC0;
108  bits<8> SSRC1;
109
110  let Inst{7-0} = SSRC0;
111  let Inst{15-8} = SSRC1;
112  let Inst{22-16} = op;
113  let Inst{31-23} = 0x17e;
114
115  let DisableEncoding = "$dst";
116  let mayLoad = 0;
117  let mayStore = 0;
118  let hasSideEffects = 0;
119  let SALU = 1;
120}
121
122class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
123   Enc32 <outs, ins , asm, pattern> {
124
125  bits <7> SDST;
126  bits <16> SIMM16;
127  
128  let Inst{15-0} = SIMM16;
129  let Inst{22-16} = SDST;
130  let Inst{27-23} = op;
131  let Inst{31-28} = 0xb; //encoding
132
133  let mayLoad = 0;
134  let mayStore = 0;
135  let hasSideEffects = 0;
136  let SALU = 1;
137}
138
139class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
140  (outs),
141  ins,
142  asm,
143  pattern > {
144
145  bits <16> SIMM16;
146
147  let Inst{15-0} = SIMM16;
148  let Inst{22-16} = op;
149  let Inst{31-23} = 0x17f; // encoding
150
151  let mayLoad = 0;
152  let mayStore = 0;
153  let hasSideEffects = 0;
154  let SALU = 1;
155}
156
157class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
158            list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
159
160  bits<7> SDST;
161  bits<7> SBASE;
162  bits<8> OFFSET;
163  
164  let Inst{7-0} = OFFSET;
165  let Inst{8} = imm;
166  let Inst{14-9} = SBASE{6-1};
167  let Inst{21-15} = SDST;
168  let Inst{26-22} = op;
169  let Inst{31-27} = 0x18; //encoding
170
171  let LGKM_CNT = 1;
172  let SMRD = 1;
173}
174
175//===----------------------------------------------------------------------===//
176// Vector ALU operations
177//===----------------------------------------------------------------------===//
178    
179let Uses = [EXEC] in {
180
181class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
182    Enc32 <outs, ins, asm, pattern> {
183
184  bits<8> VDST;
185  bits<9> SRC0;
186  
187  let Inst{8-0} = SRC0;
188  let Inst{16-9} = op;
189  let Inst{24-17} = VDST;
190  let Inst{31-25} = 0x3f; //encoding
191  
192  let mayLoad = 0;
193  let mayStore = 0;
194  let hasSideEffects = 0;
195  let UseNamedOperandTable = 1;
196  let VOP1 = 1;
197}
198
199class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
200    Enc32 <outs, ins, asm, pattern> {
201
202  bits<8> VDST;
203  bits<9> SRC0;
204  bits<8> VSRC1;
205  
206  let Inst{8-0} = SRC0;
207  let Inst{16-9} = VSRC1;
208  let Inst{24-17} = VDST;
209  let Inst{30-25} = op;
210  let Inst{31} = 0x0; //encoding
211  
212  let mayLoad = 0;
213  let mayStore = 0;
214  let hasSideEffects = 0;
215  let UseNamedOperandTable = 1;
216  let VOP2 = 1;
217}
218
219class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
220    VOP3Common <outs, ins, asm, pattern> {
221
222  bits<8> dst;
223  bits<2> src0_modifiers;
224  bits<9> src0;
225  bits<2> src1_modifiers;
226  bits<9> src1;
227  bits<2> src2_modifiers;
228  bits<9> src2;
229  bits<1> clamp;
230  bits<2> omod;
231
232  let Inst{7-0} = dst;
233  let Inst{8} = src0_modifiers{1};
234  let Inst{9} = src1_modifiers{1};
235  let Inst{10} = src2_modifiers{1};
236  let Inst{11} = clamp;
237  let Inst{25-17} = op;
238  let Inst{31-26} = 0x34; //encoding
239  let Inst{40-32} = src0;
240  let Inst{49-41} = src1;
241  let Inst{58-50} = src2;
242  let Inst{60-59} = omod;
243  let Inst{61} = src0_modifiers{0};
244  let Inst{62} = src1_modifiers{0};
245  let Inst{63} = src2_modifiers{0};
246
247}
248
249class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
250    VOP3Common <outs, ins, asm, pattern> {
251
252  bits<8> dst;
253  bits<2> src0_modifiers;
254  bits<9> src0;
255  bits<2> src1_modifiers;
256  bits<9> src1;
257  bits<2> src2_modifiers;
258  bits<9> src2;
259  bits<7> sdst;
260  bits<2> omod;
261
262  let Inst{7-0} = dst;
263  let Inst{14-8} = sdst;
264  let Inst{25-17} = op;
265  let Inst{31-26} = 0x34; //encoding
266  let Inst{40-32} = src0;
267  let Inst{49-41} = src1;
268  let Inst{58-50} = src2;
269  let Inst{60-59} = omod;
270  let Inst{61} = src0_modifiers{0};
271  let Inst{62} = src1_modifiers{0};
272  let Inst{63} = src2_modifiers{0};
273
274}
275
276class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
277    Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
278
279  bits<9> SRC0;
280  bits<8> VSRC1;
281
282  let Inst{8-0} = SRC0;
283  let Inst{16-9} = VSRC1;
284  let Inst{24-17} = op;
285  let Inst{31-25} = 0x3e;
286 
287  let DisableEncoding = "$dst";
288  let mayLoad = 0;
289  let mayStore = 0;
290  let hasSideEffects = 0;
291  let VOPC = 1;
292}
293
294class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
295    Enc32 <outs, ins, asm, pattern> {
296
297  bits<8> VDST;
298  bits<8> VSRC;
299  bits<2> ATTRCHAN;
300  bits<6> ATTR;
301
302  let Inst{7-0} = VSRC;
303  let Inst{9-8} = ATTRCHAN;
304  let Inst{15-10} = ATTR;
305  let Inst{17-16} = op;
306  let Inst{25-18} = VDST;
307  let Inst{31-26} = 0x32; // encoding
308
309  let neverHasSideEffects = 1;
310  let mayLoad = 1;
311  let mayStore = 0;
312}
313
314} // End Uses = [EXEC]
315
316//===----------------------------------------------------------------------===//
317// Vector I/O operations
318//===----------------------------------------------------------------------===//
319
320let Uses = [EXEC] in {
321
322class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
323    Enc64 <outs, ins, asm, pattern> {
324
325  bits<8> vdst;
326  bits<1> gds;
327  bits<8> addr;
328  bits<8> data0;
329  bits<8> data1;
330  bits<8> offset0;
331  bits<8> offset1;
332
333  let Inst{7-0} = offset0;
334  let Inst{15-8} = offset1;
335  let Inst{17} = gds;
336  let Inst{25-18} = op;
337  let Inst{31-26} = 0x36; //encoding
338  let Inst{39-32} = addr;
339  let Inst{47-40} = data0;
340  let Inst{55-48} = data1;
341  let Inst{63-56} = vdst;
342
343  let LGKM_CNT = 1;
344}
345
346class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
347    Enc64<outs, ins, asm, pattern> {
348
349  bits<12> offset;
350  bits<1> offen;
351  bits<1> idxen;
352  bits<1> glc;
353  bits<1> addr64;
354  bits<1> lds;
355  bits<8> vaddr;
356  bits<8> vdata;
357  bits<7> srsrc;
358  bits<1> slc;
359  bits<1> tfe;
360  bits<8> soffset;
361
362  let Inst{11-0} = offset;
363  let Inst{12} = offen;
364  let Inst{13} = idxen;
365  let Inst{14} = glc;
366  let Inst{15} = addr64;
367  let Inst{16} = lds;
368  let Inst{24-18} = op;
369  let Inst{31-26} = 0x38; //encoding
370  let Inst{39-32} = vaddr;
371  let Inst{47-40} = vdata;
372  let Inst{52-48} = srsrc{6-2};
373  let Inst{54} = slc;
374  let Inst{55} = tfe;
375  let Inst{63-56} = soffset;
376
377  let VM_CNT = 1;
378  let EXP_CNT = 1;
379
380  let neverHasSideEffects = 1;
381  let UseNamedOperandTable = 1;
382}
383
384class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
385    Enc64<outs, ins, asm, pattern> {
386
387  bits<8> VDATA;
388  bits<12> OFFSET;
389  bits<1> OFFEN;
390  bits<1> IDXEN;
391  bits<1> GLC;
392  bits<1> ADDR64;
393  bits<4> DFMT;
394  bits<3> NFMT;
395  bits<8> VADDR;
396  bits<7> SRSRC;
397  bits<1> SLC;
398  bits<1> TFE;
399  bits<8> SOFFSET;
400
401  let Inst{11-0} = OFFSET;
402  let Inst{12} = OFFEN;
403  let Inst{13} = IDXEN;
404  let Inst{14} = GLC;
405  let Inst{15} = ADDR64;
406  let Inst{18-16} = op;
407  let Inst{22-19} = DFMT;
408  let Inst{25-23} = NFMT;
409  let Inst{31-26} = 0x3a; //encoding
410  let Inst{39-32} = VADDR;
411  let Inst{47-40} = VDATA;
412  let Inst{52-48} = SRSRC{6-2};
413  let Inst{54} = SLC;
414  let Inst{55} = TFE;
415  let Inst{63-56} = SOFFSET;
416
417  let VM_CNT = 1;
418  let EXP_CNT = 1;
419
420  let neverHasSideEffects = 1;
421}
422
423class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
424    Enc64 <outs, ins, asm, pattern> {
425
426  bits<8> VDATA;
427  bits<4> DMASK;
428  bits<1> UNORM;
429  bits<1> GLC;
430  bits<1> DA;
431  bits<1> R128;
432  bits<1> TFE;
433  bits<1> LWE;
434  bits<1> SLC;
435  bits<8> VADDR;
436  bits<7> SRSRC;
437  bits<7> SSAMP; 
438
439  let Inst{11-8} = DMASK;
440  let Inst{12} = UNORM;
441  let Inst{13} = GLC;
442  let Inst{14} = DA;
443  let Inst{15} = R128;
444  let Inst{16} = TFE;
445  let Inst{17} = LWE;
446  let Inst{24-18} = op;
447  let Inst{25} = SLC;
448  let Inst{31-26} = 0x3c;
449  let Inst{39-32} = VADDR;
450  let Inst{47-40} = VDATA;
451  let Inst{52-48} = SRSRC{6-2};
452  let Inst{57-53} = SSAMP{6-2};
453
454  let VM_CNT = 1;
455  let EXP_CNT = 1;
456  let MIMG = 1;
457}
458
459def EXP : Enc64<
460  (outs),
461  (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
462       VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
463  "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
464  [] > {
465
466  bits<4> EN;
467  bits<6> TGT;
468  bits<1> COMPR;
469  bits<1> DONE;
470  bits<1> VM;
471  bits<8> VSRC0;
472  bits<8> VSRC1;
473  bits<8> VSRC2;
474  bits<8> VSRC3;
475
476  let Inst{3-0} = EN;
477  let Inst{9-4} = TGT;
478  let Inst{10} = COMPR;
479  let Inst{11} = DONE;
480  let Inst{12} = VM;
481  let Inst{31-26} = 0x3e;
482  let Inst{39-32} = VSRC0;
483  let Inst{47-40} = VSRC1;
484  let Inst{55-48} = VSRC2;
485  let Inst{63-56} = VSRC3;
486
487  let EXP_CNT = 1;
488}
489
490} // End Uses = [EXEC]
491