SIInstrFormats.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15    AMDGPUInst<outs, ins, asm, pattern> {
16
17  field bits<1> VM_CNT = 0;
18  field bits<1> EXP_CNT = 0;
19  field bits<1> LGKM_CNT = 0;
20  field bits<1> MIMG = 0;
21  field bits<1> SMRD = 0;
22  field bits<1> VOP1 = 0;
23  field bits<1> VOP2 = 0;
24  field bits<1> VOP3 = 0;
25  field bits<1> VOPC = 0;
26  field bits<1> SALU = 0;
27
28  let TSFlags{0} = VM_CNT;
29  let TSFlags{1} = EXP_CNT;
30  let TSFlags{2} = LGKM_CNT;
31  let TSFlags{3} = MIMG;
32  let TSFlags{4} = SMRD;
33  let TSFlags{5} = VOP1;
34  let TSFlags{6} = VOP2;
35  let TSFlags{7} = VOP3;
36  let TSFlags{8} = VOPC;
37  let TSFlags{9} = SALU;
38}
39
40class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
41    InstSI <outs, ins, asm, pattern> {
42
43  field bits<32> Inst;
44  let Size = 4;
45}
46
47class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
48    InstSI <outs, ins, asm, pattern> {
49
50  field bits<64> Inst;
51  let Size = 8;
52}
53
54//===----------------------------------------------------------------------===//
55// Scalar operations
56//===----------------------------------------------------------------------===//
57
58class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
59    Enc32<outs, ins, asm, pattern> {
60
61  bits<7> SDST;
62  bits<8> SSRC0;
63
64  let Inst{7-0} = SSRC0;
65  let Inst{15-8} = op;
66  let Inst{22-16} = SDST;
67  let Inst{31-23} = 0x17d; //encoding;
68
69  let mayLoad = 0;
70  let mayStore = 0;
71  let hasSideEffects = 0;
72  let SALU = 1;
73}
74
75class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
76    Enc32 <outs, ins, asm, pattern> {
77  
78  bits<7> SDST;
79  bits<8> SSRC0;
80  bits<8> SSRC1;
81
82  let Inst{7-0} = SSRC0;
83  let Inst{15-8} = SSRC1;
84  let Inst{22-16} = SDST;
85  let Inst{29-23} = op;
86  let Inst{31-30} = 0x2; // encoding
87
88  let mayLoad = 0;
89  let mayStore = 0;
90  let hasSideEffects = 0;
91  let SALU = 1;
92}
93
94class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
95  Enc32<outs, ins, asm, pattern> {
96
97  bits<8> SSRC0;
98  bits<8> SSRC1;
99
100  let Inst{7-0} = SSRC0;
101  let Inst{15-8} = SSRC1;
102  let Inst{22-16} = op;
103  let Inst{31-23} = 0x17e;
104
105  let DisableEncoding = "$dst";
106  let mayLoad = 0;
107  let mayStore = 0;
108  let hasSideEffects = 0;
109  let SALU = 1;
110}
111
112class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
113   Enc32 <outs, ins , asm, pattern> {
114
115  bits <7> SDST;
116  bits <16> SIMM16;
117  
118  let Inst{15-0} = SIMM16;
119  let Inst{22-16} = SDST;
120  let Inst{27-23} = op;
121  let Inst{31-28} = 0xb; //encoding
122
123  let mayLoad = 0;
124  let mayStore = 0;
125  let hasSideEffects = 0;
126  let SALU = 1;
127}
128
129class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
130  (outs),
131  ins,
132  asm,
133  pattern > {
134
135  bits <16> SIMM16;
136
137  let Inst{15-0} = SIMM16;
138  let Inst{22-16} = op;
139  let Inst{31-23} = 0x17f; // encoding
140
141  let mayLoad = 0;
142  let mayStore = 0;
143  let hasSideEffects = 0;
144  let SALU = 1;
145}
146
147class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
148            list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
149
150  bits<7> SDST;
151  bits<7> SBASE;
152  bits<8> OFFSET;
153  
154  let Inst{7-0} = OFFSET;
155  let Inst{8} = imm;
156  let Inst{14-9} = SBASE{6-1};
157  let Inst{21-15} = SDST;
158  let Inst{26-22} = op;
159  let Inst{31-27} = 0x18; //encoding
160
161  let LGKM_CNT = 1;
162  let SMRD = 1;
163}
164
165//===----------------------------------------------------------------------===//
166// Vector ALU operations
167//===----------------------------------------------------------------------===//
168    
169let Uses = [EXEC] in {
170
171class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
172    Enc32 <outs, ins, asm, pattern> {
173
174  bits<8> VDST;
175  bits<9> SRC0;
176  
177  let Inst{8-0} = SRC0;
178  let Inst{16-9} = op;
179  let Inst{24-17} = VDST;
180  let Inst{31-25} = 0x3f; //encoding
181  
182  let mayLoad = 0;
183  let mayStore = 0;
184  let hasSideEffects = 0;
185  let UseNamedOperandTable = 1;
186  let VOP1 = 1;
187}
188
189class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
190    Enc32 <outs, ins, asm, pattern> {
191
192  bits<8> VDST;
193  bits<9> SRC0;
194  bits<8> VSRC1;
195  
196  let Inst{8-0} = SRC0;
197  let Inst{16-9} = VSRC1;
198  let Inst{24-17} = VDST;
199  let Inst{30-25} = op;
200  let Inst{31} = 0x0; //encoding
201  
202  let mayLoad = 0;
203  let mayStore = 0;
204  let hasSideEffects = 0;
205  let UseNamedOperandTable = 1;
206  let VOP2 = 1;
207}
208
209class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
210    Enc64 <outs, ins, asm, pattern> {
211
212  bits<8> dst;
213  bits<9> src0;
214  bits<9> src1;
215  bits<9> src2;
216  bits<3> abs;
217  bits<1> clamp;
218  bits<2> omod;
219  bits<3> neg;
220
221  let Inst{7-0} = dst;
222  let Inst{10-8} = abs;
223  let Inst{11} = clamp;
224  let Inst{25-17} = op;
225  let Inst{31-26} = 0x34; //encoding
226  let Inst{40-32} = src0;
227  let Inst{49-41} = src1;
228  let Inst{58-50} = src2;
229  let Inst{60-59} = omod;
230  let Inst{63-61} = neg;
231  
232  let mayLoad = 0;
233  let mayStore = 0;
234  let hasSideEffects = 0;
235  let UseNamedOperandTable = 1;
236  let VOP3 = 1;
237}
238
239class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
240    Enc64 <outs, ins, asm, pattern> {
241
242  bits<8> dst;
243  bits<9> src0;
244  bits<9> src1;
245  bits<9> src2;
246  bits<7> sdst;
247  bits<2> omod;
248  bits<3> neg;
249
250  let Inst{7-0} = dst;
251  let Inst{14-8} = sdst;
252  let Inst{25-17} = op;
253  let Inst{31-26} = 0x34; //encoding
254  let Inst{40-32} = src0;
255  let Inst{49-41} = src1;
256  let Inst{58-50} = src2;
257  let Inst{60-59} = omod;
258  let Inst{63-61} = neg;
259
260  let mayLoad = 0;
261  let mayStore = 0;
262  let hasSideEffects = 0;
263  let UseNamedOperandTable = 1;
264  let VOP3 = 1;
265}
266
267class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
268    Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
269
270  bits<9> SRC0;
271  bits<8> VSRC1;
272
273  let Inst{8-0} = SRC0;
274  let Inst{16-9} = VSRC1;
275  let Inst{24-17} = op;
276  let Inst{31-25} = 0x3e;
277 
278  let DisableEncoding = "$dst";
279  let mayLoad = 0;
280  let mayStore = 0;
281  let hasSideEffects = 0;
282  let VOPC = 1;
283}
284
285class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
286    Enc32 <outs, ins, asm, pattern> {
287
288  bits<8> VDST;
289  bits<8> VSRC;
290  bits<2> ATTRCHAN;
291  bits<6> ATTR;
292
293  let Inst{7-0} = VSRC;
294  let Inst{9-8} = ATTRCHAN;
295  let Inst{15-10} = ATTR;
296  let Inst{17-16} = op;
297  let Inst{25-18} = VDST;
298  let Inst{31-26} = 0x32; // encoding
299
300  let neverHasSideEffects = 1;
301  let mayLoad = 1;
302  let mayStore = 0;
303}
304
305} // End Uses = [EXEC]
306
307//===----------------------------------------------------------------------===//
308// Vector I/O operations
309//===----------------------------------------------------------------------===//
310
311let Uses = [EXEC] in {
312
313class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
314    Enc64 <outs, ins, asm, pattern> {
315
316  bits<8> vdst;
317  bits<1> gds;
318  bits<8> addr;
319  bits<8> data0;
320  bits<8> data1;
321  bits<8> offset0;
322  bits<8> offset1;
323
324  let Inst{7-0} = offset0;
325  let Inst{15-8} = offset1;
326  let Inst{17} = gds;
327  let Inst{25-18} = op;
328  let Inst{31-26} = 0x36; //encoding
329  let Inst{39-32} = addr;
330  let Inst{47-40} = data0;
331  let Inst{55-48} = data1;
332  let Inst{63-56} = vdst;
333
334  let LGKM_CNT = 1;
335}
336
337class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
338    Enc64<outs, ins, asm, pattern> {
339
340  bits<12> offset;
341  bits<1> offen;
342  bits<1> idxen;
343  bits<1> glc;
344  bits<1> addr64;
345  bits<1> lds;
346  bits<8> vaddr;
347  bits<8> vdata;
348  bits<7> srsrc;
349  bits<1> slc;
350  bits<1> tfe;
351  bits<8> soffset;
352
353  let Inst{11-0} = offset;
354  let Inst{12} = offen;
355  let Inst{13} = idxen;
356  let Inst{14} = glc;
357  let Inst{15} = addr64;
358  let Inst{16} = lds;
359  let Inst{24-18} = op;
360  let Inst{31-26} = 0x38; //encoding
361  let Inst{39-32} = vaddr;
362  let Inst{47-40} = vdata;
363  let Inst{52-48} = srsrc{6-2};
364  let Inst{54} = slc;
365  let Inst{55} = tfe;
366  let Inst{63-56} = soffset;
367
368  let VM_CNT = 1;
369  let EXP_CNT = 1;
370
371  let neverHasSideEffects = 1;
372  let UseNamedOperandTable = 1;
373}
374
375class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
376    Enc64<outs, ins, asm, pattern> {
377
378  bits<8> VDATA;
379  bits<12> OFFSET;
380  bits<1> OFFEN;
381  bits<1> IDXEN;
382  bits<1> GLC;
383  bits<1> ADDR64;
384  bits<4> DFMT;
385  bits<3> NFMT;
386  bits<8> VADDR;
387  bits<7> SRSRC;
388  bits<1> SLC;
389  bits<1> TFE;
390  bits<8> SOFFSET;
391
392  let Inst{11-0} = OFFSET;
393  let Inst{12} = OFFEN;
394  let Inst{13} = IDXEN;
395  let Inst{14} = GLC;
396  let Inst{15} = ADDR64;
397  let Inst{18-16} = op;
398  let Inst{22-19} = DFMT;
399  let Inst{25-23} = NFMT;
400  let Inst{31-26} = 0x3a; //encoding
401  let Inst{39-32} = VADDR;
402  let Inst{47-40} = VDATA;
403  let Inst{52-48} = SRSRC{6-2};
404  let Inst{54} = SLC;
405  let Inst{55} = TFE;
406  let Inst{63-56} = SOFFSET;
407
408  let VM_CNT = 1;
409  let EXP_CNT = 1;
410
411  let neverHasSideEffects = 1;
412}
413
414class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
415    Enc64 <outs, ins, asm, pattern> {
416
417  bits<8> VDATA;
418  bits<4> DMASK;
419  bits<1> UNORM;
420  bits<1> GLC;
421  bits<1> DA;
422  bits<1> R128;
423  bits<1> TFE;
424  bits<1> LWE;
425  bits<1> SLC;
426  bits<8> VADDR;
427  bits<7> SRSRC;
428  bits<7> SSAMP; 
429
430  let Inst{11-8} = DMASK;
431  let Inst{12} = UNORM;
432  let Inst{13} = GLC;
433  let Inst{14} = DA;
434  let Inst{15} = R128;
435  let Inst{16} = TFE;
436  let Inst{17} = LWE;
437  let Inst{24-18} = op;
438  let Inst{25} = SLC;
439  let Inst{31-26} = 0x3c;
440  let Inst{39-32} = VADDR;
441  let Inst{47-40} = VDATA;
442  let Inst{52-48} = SRSRC{6-2};
443  let Inst{57-53} = SSAMP{6-2};
444
445  let VM_CNT = 1;
446  let EXP_CNT = 1;
447  let MIMG = 1;
448}
449
450def EXP : Enc64<
451  (outs),
452  (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
453       VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
454  "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
455  [] > {
456
457  bits<4> EN;
458  bits<6> TGT;
459  bits<1> COMPR;
460  bits<1> DONE;
461  bits<1> VM;
462  bits<8> VSRC0;
463  bits<8> VSRC1;
464  bits<8> VSRC2;
465  bits<8> VSRC3;
466
467  let Inst{3-0} = EN;
468  let Inst{9-4} = TGT;
469  let Inst{10} = COMPR;
470  let Inst{11} = DONE;
471  let Inst{12} = VM;
472  let Inst{31-26} = 0x3e;
473  let Inst{39-32} = VSRC0;
474  let Inst{47-40} = VSRC1;
475  let Inst{55-48} = VSRC2;
476  let Inst{63-56} = VSRC3;
477
478  let EXP_CNT = 1;
479}
480
481} // End Uses = [EXEC]
482