SIInstrInfo.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for SIInstrInfo.
12//
13//===----------------------------------------------------------------------===//
14
15
16#ifndef SIINSTRINFO_H
17#define SIINSTRINFO_H
18
19#include "AMDGPUInstrInfo.h"
20#include "SIRegisterInfo.h"
21
22namespace llvm {
23
24class SIInstrInfo : public AMDGPUInstrInfo {
25private:
26  const SIRegisterInfo RI;
27
28  unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29                              MachineRegisterInfo &MRI,
30                              MachineOperand &SuperReg,
31                              const TargetRegisterClass *SuperRC,
32                              unsigned SubIdx,
33                              const TargetRegisterClass *SubRC) const;
34  MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
35                                         MachineRegisterInfo &MRI,
36                                         MachineOperand &SuperReg,
37                                         const TargetRegisterClass *SuperRC,
38                                         unsigned SubIdx,
39                                         const TargetRegisterClass *SubRC) const;
40
41  unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
42                         MachineBasicBlock::iterator MI,
43                         MachineRegisterInfo &MRI,
44                         const TargetRegisterClass *RC,
45                         const MachineOperand &Op) const;
46
47  void splitScalar64BitOp(SmallVectorImpl<MachineInstr *> & Worklist,
48                          MachineInstr *Inst, unsigned Opcode) const;
49
50
51public:
52  explicit SIInstrInfo(AMDGPUTargetMachine &tm);
53
54  const SIRegisterInfo &getRegisterInfo() const {
55    return RI;
56  }
57
58  virtual void copyPhysReg(MachineBasicBlock &MBB,
59                           MachineBasicBlock::iterator MI, DebugLoc DL,
60                           unsigned DestReg, unsigned SrcReg,
61                           bool KillSrc) const;
62
63  void storeRegToStackSlot(MachineBasicBlock &MBB,
64                           MachineBasicBlock::iterator MI,
65                           unsigned SrcReg, bool isKill, int FrameIndex,
66                           const TargetRegisterClass *RC,
67                           const TargetRegisterInfo *TRI) const;
68
69  void loadRegFromStackSlot(MachineBasicBlock &MBB,
70                            MachineBasicBlock::iterator MI,
71                            unsigned DestReg, int FrameIndex,
72                            const TargetRegisterClass *RC,
73                            const TargetRegisterInfo *TRI) const;
74
75  unsigned commuteOpcode(unsigned Opcode) const;
76
77  virtual MachineInstr *commuteInstruction(MachineInstr *MI,
78                                           bool NewMI=false) const;
79
80  bool isTriviallyReMaterializable(const MachineInstr *MI,
81                                   AliasAnalysis *AA = 0) const;
82
83  virtual unsigned getIEQOpcode() const {
84    llvm_unreachable("Unimplemented");
85  }
86
87  MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
88                              MachineBasicBlock::iterator I,
89                              unsigned DstReg, unsigned SrcReg) const;
90  virtual bool isMov(unsigned Opcode) const;
91
92  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
93  bool isDS(uint16_t Opcode) const;
94  int isMIMG(uint16_t Opcode) const;
95  int isSMRD(uint16_t Opcode) const;
96  bool isVOP1(uint16_t Opcode) const;
97  bool isVOP2(uint16_t Opcode) const;
98  bool isVOP3(uint16_t Opcode) const;
99  bool isVOPC(uint16_t Opcode) const;
100  bool isInlineConstant(const APInt &Imm) const;
101  bool isInlineConstant(const MachineOperand &MO) const;
102  bool isLiteralConstant(const MachineOperand &MO) const;
103
104  virtual bool verifyInstruction(const MachineInstr *MI,
105                                 StringRef &ErrInfo) const;
106
107  bool isSALUInstr(const MachineInstr &MI) const;
108  static unsigned getVALUOp(const MachineInstr &MI);
109
110  bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
111
112  /// \brief Return the correct register class for \p OpNo.  For target-specific
113  /// instructions, this will return the register class that has been defined
114  /// in tablegen.  For generic instructions, like REG_SEQUENCE it will return
115  /// the register class of its machine operand.
116  /// to infer the correct register class base on the other operands.
117  const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
118                                           unsigned OpNo) const;\
119
120  /// \returns true if it is legal for the operand at index \p OpNo
121  /// to read a VGPR.
122  bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
123
124  /// \brief Legalize the \p OpIndex operand of this instruction by inserting
125  /// a MOV.  For example:
126  /// ADD_I32_e32 VGPR0, 15
127  /// to
128  /// MOV VGPR1, 15
129  /// ADD_I32_e32 VGPR0, VGPR1
130  ///
131  /// If the operand being legalized is a register, then a COPY will be used
132  /// instead of MOV.
133  void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
134
135  /// \brief Legalize all operands in this instruction.  This function may
136  /// create new instruction and insert them before \p MI.
137  void legalizeOperands(MachineInstr *MI) const;
138
139  /// \brief Replace this instruction's opcode with the equivalent VALU
140  /// opcode.  This function will also move the users of \p MI to the
141  /// VALU if necessary.
142  void moveToVALU(MachineInstr &MI) const;
143
144  virtual unsigned calculateIndirectAddress(unsigned RegIndex,
145                                            unsigned Channel) const;
146
147  virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
148
149  virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
150                                                 MachineBasicBlock::iterator I,
151                                                 unsigned ValueReg,
152                                                 unsigned Address,
153                                                 unsigned OffsetReg) const;
154
155  virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
156                                                MachineBasicBlock::iterator I,
157                                                unsigned ValueReg,
158                                                unsigned Address,
159                                                unsigned OffsetReg) const;
160  void reserveIndirectRegisters(BitVector &Reserved,
161                                const MachineFunction &MF) const;
162
163  void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
164              unsigned SavReg, unsigned IndexReg) const;
165};
166
167namespace AMDGPU {
168
169  int getVOPe64(uint16_t Opcode);
170  int getCommuteRev(uint16_t Opcode);
171  int getCommuteOrig(uint16_t Opcode);
172
173  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
174
175
176} // End namespace AMDGPU
177
178} // End namespace llvm
179
180namespace SIInstrFlags {
181  enum Flags {
182    // First 4 bits are the instruction encoding
183    VM_CNT = 1 << 0,
184    EXP_CNT = 1 << 1,
185    LGKM_CNT = 1 << 2
186  };
187}
188
189#endif //SIINSTRINFO_H
190