SIInstrInfo.h revision b52bf6a3b31596a309f4b12884522e9b4a344654 
1//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for SIInstrInfo.
12//
13//===----------------------------------------------------------------------===//
14
15
16#ifndef SIINSTRINFO_H
17#define SIINSTRINFO_H
18
19#include "AMDGPUInstrInfo.h"
20#include "SIRegisterInfo.h"
21
22namespace llvm {
23
24class SIInstrInfo : public AMDGPUInstrInfo {
25private:
26  const SIRegisterInfo RI;
27
28public:
29  explicit SIInstrInfo(AMDGPUTargetMachine &tm);
30
31  const SIRegisterInfo &getRegisterInfo() const;
32
33  virtual void copyPhysReg(MachineBasicBlock &MBB,
34                           MachineBasicBlock::iterator MI, DebugLoc DL,
35                           unsigned DestReg, unsigned SrcReg,
36                           bool KillSrc) const;
37
38  unsigned commuteOpcode(unsigned Opcode) const;
39
40  virtual MachineInstr *commuteInstruction(MachineInstr *MI,
41                                           bool NewMI=false) const;
42
43  virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
44  MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
45                              MachineBasicBlock::iterator I,
46                              unsigned DstReg, unsigned SrcReg) const;
47  virtual bool isMov(unsigned Opcode) const;
48
49  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
50  int isMIMG(uint16_t Opcode) const;
51  int isSMRD(uint16_t Opcode) const;
52  bool isVOP1(uint16_t Opcode) const;
53  bool isVOP2(uint16_t Opcode) const;
54  bool isVOP3(uint16_t Opcode) const;
55  bool isVOPC(uint16_t Opcode) const;
56  bool isInlineConstant(const MachineOperand &MO) const;
57  bool isLiteralConstant(const MachineOperand &MO) const;
58
59  virtual bool verifyInstruction(const MachineInstr *MI,
60                                 StringRef &ErrInfo) const;
61  virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
62
63  virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
64
65  bool isSALUInstr(const MachineInstr &MI) const;
66  unsigned getVALUOp(const MachineInstr &MI) const;
67  bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
68
69  /// \brief Return the correct register class for \p OpNo.  For target-specific
70  /// instructions, this will return the register class that has been defined
71  /// in tablegen.  For generic instructions, like REG_SEQUENCE it will return
72  /// the register class of its machine operand.
73  /// to infer the correct register class base on the other operands.
74  const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
75                                           unsigned OpNo) const;\
76
77  /// \returns true if it is legal for the operand at index \p OpNo
78  /// to read a VGPR.
79  bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
80
81  /// \brief Legalize the \p OpIndex operand of this instruction by inserting
82  /// a MOV.  For example:
83  /// ADD_I32_e32 VGPR0, 15
84  /// to
85  /// MOV VGPR1, 15
86  /// ADD_I32_e32 VGPR0, VGPR1
87  ///
88  /// If the operand being legalized is a register, then a COPY will be used
89  /// instead of MOV.
90  void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
91
92  /// \brief Legalize all operands in this instruction.  This function may
93  /// create new instruction and insert them before \p MI.
94  void legalizeOperands(MachineInstr *MI) const;
95
96  /// \brief Replace this instruction's opcode with the equivalent VALU
97  /// opcode.  This function will also move the users of \p MI to the
98  /// VALU if necessary.
99  void moveToVALU(MachineInstr &MI) const;
100
101  virtual unsigned calculateIndirectAddress(unsigned RegIndex,
102                                            unsigned Channel) const;
103
104  virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
105
106  virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
107                                                 MachineBasicBlock::iterator I,
108                                                 unsigned ValueReg,
109                                                 unsigned Address,
110                                                 unsigned OffsetReg) const;
111
112  virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
113                                                MachineBasicBlock::iterator I,
114                                                unsigned ValueReg,
115                                                unsigned Address,
116                                                unsigned OffsetReg) const;
117  };
118
119namespace AMDGPU {
120
121  int getVOPe64(uint16_t Opcode);
122  int getCommuteRev(uint16_t Opcode);
123  int getCommuteOrig(uint16_t Opcode);
124
125} // End namespace AMDGPU
126
127} // End namespace llvm
128
129namespace SIInstrFlags {
130  enum Flags {
131    // First 4 bits are the instruction encoding
132    VM_CNT = 1 << 0,
133    EXP_CNT = 1 << 1,
134    LGKM_CNT = 1 << 2
135  };
136}
137
138#endif //SIINSTRINFO_H
139