SIInstructions.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def SendMsgImm : Operand<i32> { 26 let PrintMethod = "printSendMsg"; 27} 28 29def isSI : Predicate<"Subtarget.getGeneration() " 30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; 31 32def isCI : Predicate<"Subtarget.getGeneration() " 33 ">= AMDGPUSubtarget::SEA_ISLANDS">; 34 35def WAIT_FLAG : InstFlag<"printWaitFlag">; 36 37let Predicates = [isSI] in { 38 39let neverHasSideEffects = 1 in { 40 41let isMoveImm = 1 in { 42def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 43def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 44def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 45def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 46} // End isMoveImm = 1 47 48def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 49def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 50def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 51def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 52def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 53def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 54} // End neverHasSideEffects = 1 55 56////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 57////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 58////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 59////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 60////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 61////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 62////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 63////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 64//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 65//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 66def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 67//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 68//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 69//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 70////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 71////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 72////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 73////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 74def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 75def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 76def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 77def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 78 79let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 80 81def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 82def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 83def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 84def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 85def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 86def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 87def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 88def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 89 90} // End hasSideEffects = 1 91 92def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 93def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 94def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 95def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 96def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 97def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 98//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 99def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 100def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 101def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 102def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 103def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 104 105/* 106This instruction is disabled for now until we can figure out how to teach 107the instruction selector to correctly use the S_CMP* vs V_CMP* 108instructions. 109 110When this instruction is enabled the code generator sometimes produces this 111invalid sequence: 112 113SCC = S_CMPK_EQ_I32 SGPR0, imm 114VCC = COPY SCC 115VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 116 117def S_CMPK_EQ_I32 : SOPK < 118 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 119 "S_CMPK_EQ_I32", 120 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 121>; 122*/ 123 124let isCompare = 1 in { 125def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 126def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 127def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 128def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 129def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 130def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 131def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 132def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 133def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 134def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 135def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 136} // End isCompare = 1 137 138let Defs = [SCC], isCommutable = 1 in { 139 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 140 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 141} 142 143//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 144def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 145def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 146def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 147//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 148//def EXP : EXP_ <0x00000000, "EXP", []>; 149 150let isCompare = 1 in { 151 152defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 153defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>; 154defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>; 155defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>; 156defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>; 157defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">; 158defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>; 159defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>; 160defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>; 161defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 162defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 163defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 164defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 165defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>; 166defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 167defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 168 169let hasSideEffects = 1, Defs = [EXEC] in { 170 171defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 172defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 173defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 174defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 175defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 176defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 177defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 178defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 179defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 180defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 181defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 182defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 183defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 184defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 185defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 186defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 187 188} // End hasSideEffects = 1, Defs = [EXEC] 189 190defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 191defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>; 192defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>; 193defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>; 194defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>; 195defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 196defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>; 197defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>; 198defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>; 199defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 200defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 201defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 202defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 203defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>; 204defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 205defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 206 207let hasSideEffects = 1, Defs = [EXEC] in { 208 209defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 210defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 211defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 212defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 213defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 214defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 215defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 216defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 217defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 218defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 219defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 220defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 221defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 222defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 223defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 224defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 225 226} // End hasSideEffects = 1, Defs = [EXEC] 227 228defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 229defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 230defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 231defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 232defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 233defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 234defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 235defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 236defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 237defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 238defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 239defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 240defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 241defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 242defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 243defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 244 245let hasSideEffects = 1, Defs = [EXEC] in { 246 247defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 248defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 249defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 250defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 251defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 252defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 253defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 254defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 255defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 256defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 257defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 258defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 259defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 260defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 261defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 262defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 263 264} // End hasSideEffects = 1, Defs = [EXEC] 265 266defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 267defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 268defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 269defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 270defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 271defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 272defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 273defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 274defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 275defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 276defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 277defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 278defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 279defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 280defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 281defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 282 283let hasSideEffects = 1, Defs = [EXEC] in { 284 285defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 286defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 287defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 288defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 289defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 290defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 291defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 292defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 293defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 294defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 295defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 296defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 297defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 298defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 299defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 300defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 301 302} // End hasSideEffects = 1, Defs = [EXEC] 303 304defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 305defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>; 306defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 307defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>; 308defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>; 309defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 310defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>; 311defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 312 313let hasSideEffects = 1, Defs = [EXEC] in { 314 315defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 316defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 317defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 318defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 319defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 320defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 321defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 322defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 323 324} // End hasSideEffects = 1, Defs = [EXEC] 325 326defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 327defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>; 328defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>; 329defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>; 330defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>; 331defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>; 332defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>; 333defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 334 335let hasSideEffects = 1, Defs = [EXEC] in { 336 337defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 338defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 339defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 340defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 341defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 342defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 343defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 344defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 345 346} // End hasSideEffects = 1, Defs = [EXEC] 347 348defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 349defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>; 350defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>; 351defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>; 352defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>; 353defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>; 354defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>; 355defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 356 357let hasSideEffects = 1, Defs = [EXEC] in { 358 359defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 360defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 361defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 362defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 363defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 364defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 365defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 366defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 367 368} // End hasSideEffects = 1, Defs = [EXEC] 369 370defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 371defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>; 372defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>; 373defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>; 374defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>; 375defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>; 376defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>; 377defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 378 379let hasSideEffects = 1, Defs = [EXEC] in { 380 381defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 382defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 383defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 384defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 385defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 386defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 387defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 388defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 389 390} // End hasSideEffects = 1, Defs = [EXEC] 391 392defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 393 394let hasSideEffects = 1, Defs = [EXEC] in { 395defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 396} // End hasSideEffects = 1, Defs = [EXEC] 397 398defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 399 400let hasSideEffects = 1, Defs = [EXEC] in { 401defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 402} // End hasSideEffects = 1, Defs = [EXEC] 403 404} // End isCompare = 1 405 406def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>; 407def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>; 408def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; 409def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>; 410def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>; 411def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>; 412 413def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>; 414def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>; 415def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>; 416def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>; 417def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; 418def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>; 419 420// 2 forms. 421def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>; 422def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>; 423 424def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>; 425def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>; 426 427// TODO: DS_READ2ST64_B32, DS_READ2ST64_B64, 428// DS_WRITE2ST64_B32, DS_WRITE2ST64_B64 429 430 431//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 432//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 433//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 434defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 435//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 436//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 437//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 438//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 439defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; 440defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>; 441defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>; 442defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>; 443defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 444defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 445defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 446 447def BUFFER_STORE_BYTE : MUBUF_Store_Helper < 448 0x00000018, "BUFFER_STORE_BYTE", VReg_32 449>; 450 451def BUFFER_STORE_SHORT : MUBUF_Store_Helper < 452 0x0000001a, "BUFFER_STORE_SHORT", VReg_32 453>; 454 455def BUFFER_STORE_DWORD : MUBUF_Store_Helper < 456 0x0000001c, "BUFFER_STORE_DWORD", VReg_32 457>; 458 459def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 460 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64 461>; 462 463def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 464 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128 465>; 466//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 467//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 468//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 469//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 470//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 471//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 472//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 473//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 474//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 475//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 476//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 477//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 478//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 479//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 480//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 481//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 482//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 483//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 484//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 485//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 486//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 487//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 488//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 489//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 490//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 491//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 492//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 493//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 494//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 495//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 496//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 497//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 498//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 499//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 500//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 501//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 502//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 503//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 504//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 505def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 506def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; 507def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; 508def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; 509def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; 510 511let mayLoad = 1 in { 512 513// We are using the SGPR_32 and not the SReg_32 register class for 32-bit 514// SMRD instructions, because the SGPR_32 register class does not include M0 515// and writing to M0 from an SMRD instruction will hang the GPU. 516defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>; 517defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 518defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 519defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 520defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 521 522defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 523 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32 524>; 525 526defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 527 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 528>; 529 530defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 531 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 532>; 533 534defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 535 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 536>; 537 538defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 539 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 540>; 541 542} // mayLoad = 1 543 544//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 545//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 546defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">; 547defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">; 548//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 549//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 550//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 551//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 552//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 553//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 554//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 555//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 556defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">; 557//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 558//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 559//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 560//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 561//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 562//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 563//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 564//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 565//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 566//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 567//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 568//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 569//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 570//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 571//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 572//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 573//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 574defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; 575//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 576defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; 577//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 578defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; 579defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; 580//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 581//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 582defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; 583//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 584defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; 585//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 586defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; 587defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; 588//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 589//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 590//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 591//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 592//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 593//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 594//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 595//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 596//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 597//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 598//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 599//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 600//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 601//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 602//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 603//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 604//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 605//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 606//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 607//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 608//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 609//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 610//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 611//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 612//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 613//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 614//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 615//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 616//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 617//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 618//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 619//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 620//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 621//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 622//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 623//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 624//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 625//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 626//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 627//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 628//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 629//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 630//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 631//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 632//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 633//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 634//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 635//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 636//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 637//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 638//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 639//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 640//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 641//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 642 643 644let neverHasSideEffects = 1, isMoveImm = 1 in { 645defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 646} // End neverHasSideEffects = 1, isMoveImm = 1 647 648let Uses = [EXEC] in { 649 650def V_READFIRSTLANE_B32 : VOP1 < 651 0x00000002, 652 (outs SReg_32:$vdst), 653 (ins VReg_32:$src0), 654 "V_READFIRSTLANE_B32 $vdst, $src0", 655 [] 656>; 657 658} 659 660defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", 661 [(set i32:$dst, (fp_to_sint f64:$src0))] 662>; 663defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32", 664 [(set f64:$dst, (sint_to_fp i32:$src0))] 665>; 666defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 667 [(set f32:$dst, (sint_to_fp i32:$src0))] 668>; 669defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", 670 [(set f32:$dst, (uint_to_fp i32:$src0))] 671>; 672defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", 673 [(set i32:$dst, (fp_to_uint f32:$src0))] 674>; 675defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 676 [(set i32:$dst, (fp_to_sint f32:$src0))] 677>; 678defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 679////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 680//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 681//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 682//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 683//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 684defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64", 685 [(set f32:$dst, (fround f64:$src0))] 686>; 687defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32", 688 [(set f64:$dst, (fextend f32:$src0))] 689>; 690//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 691//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 692//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 693//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 694//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 695//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 696defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 697 [(set f32:$dst, (AMDGPUfract f32:$src0))] 698>; 699defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", 700 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] 701>; 702defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 703 [(set f32:$dst, (fceil f32:$src0))] 704>; 705defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 706 [(set f32:$dst, (frint f32:$src0))] 707>; 708defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 709 [(set f32:$dst, (ffloor f32:$src0))] 710>; 711defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 712 [(set f32:$dst, (fexp2 f32:$src0))] 713>; 714defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 715defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 716 [(set f32:$dst, (flog2 f32:$src0))] 717>; 718defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 719defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 720defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 721 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 722>; 723defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 724defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 725defm V_RSQ_LEGACY_F32 : VOP1_32 < 726 0x0000002d, "V_RSQ_LEGACY_F32", 727 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] 728>; 729defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 730defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", 731 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))] 732>; 733defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 734defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 735defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 736defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", 737 [(set f32:$dst, (fsqrt f32:$src0))] 738>; 739defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", 740 [(set f64:$dst, (fsqrt f64:$src0))] 741>; 742defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 743defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 744defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 745defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 746defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 747defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 748defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 749//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 750defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 751defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 752//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 753defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 754//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 755defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 756defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 757defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 758 759def V_INTERP_P1_F32 : VINTRP < 760 0x00000000, 761 (outs VReg_32:$dst), 762 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 763 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 764 []> { 765 let DisableEncoding = "$m0"; 766} 767 768def V_INTERP_P2_F32 : VINTRP < 769 0x00000001, 770 (outs VReg_32:$dst), 771 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 772 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 773 []> { 774 775 let Constraints = "$src0 = $dst"; 776 let DisableEncoding = "$src0,$m0"; 777 778} 779 780def V_INTERP_MOV_F32 : VINTRP < 781 0x00000002, 782 (outs VReg_32:$dst), 783 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 784 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 785 []> { 786 let DisableEncoding = "$m0"; 787} 788 789//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 790 791let isTerminator = 1 in { 792 793def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 794 [(IL_retflag)]> { 795 let SIMM16 = 0; 796 let isBarrier = 1; 797 let hasCtrlDep = 1; 798} 799 800let isBranch = 1 in { 801def S_BRANCH : SOPP < 802 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 803 [(br bb:$target)]> { 804 let isBarrier = 1; 805} 806 807let DisableEncoding = "$scc" in { 808def S_CBRANCH_SCC0 : SOPP < 809 0x00000004, (ins brtarget:$target, SCCReg:$scc), 810 "S_CBRANCH_SCC0 $target", [] 811>; 812def S_CBRANCH_SCC1 : SOPP < 813 0x00000005, (ins brtarget:$target, SCCReg:$scc), 814 "S_CBRANCH_SCC1 $target", 815 [] 816>; 817} // End DisableEncoding = "$scc" 818 819def S_CBRANCH_VCCZ : SOPP < 820 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 821 "S_CBRANCH_VCCZ $target", 822 [] 823>; 824def S_CBRANCH_VCCNZ : SOPP < 825 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 826 "S_CBRANCH_VCCNZ $target", 827 [] 828>; 829 830let DisableEncoding = "$exec" in { 831def S_CBRANCH_EXECZ : SOPP < 832 0x00000008, (ins brtarget:$target, EXECReg:$exec), 833 "S_CBRANCH_EXECZ $target", 834 [] 835>; 836def S_CBRANCH_EXECNZ : SOPP < 837 0x00000009, (ins brtarget:$target, EXECReg:$exec), 838 "S_CBRANCH_EXECNZ $target", 839 [] 840>; 841} // End DisableEncoding = "$exec" 842 843 844} // End isBranch = 1 845} // End isTerminator = 1 846 847let hasSideEffects = 1 in { 848def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", 849 [(int_AMDGPU_barrier_local)] 850> { 851 let SIMM16 = 0; 852 let isBarrier = 1; 853 let hasCtrlDep = 1; 854 let mayLoad = 1; 855 let mayStore = 1; 856} 857 858def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16", 859 [] 860>; 861//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 862//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 863//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 864 865let Uses = [EXEC] in { 866 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16", 867 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)] 868 > { 869 let DisableEncoding = "$m0"; 870 } 871} // End Uses = [EXEC] 872 873//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 874//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 875//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 876//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 877//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 878//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 879} // End hasSideEffects 880 881def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 882 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 883 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 884 [] 885>{ 886 let DisableEncoding = "$vcc"; 887} 888 889def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 890 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 891 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 892 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 893 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] 894>; 895 896//f32 pattern for V_CNDMASK_B32_e64 897def : Pat < 898 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 899 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 900>; 901 902def : Pat < 903 (i32 (trunc i64:$val)), 904 (EXTRACT_SUBREG $val, sub0) 905>; 906 907def V_READLANE_B32 : VOP2 < 908 0x00000001, 909 (outs SReg_32:$vdst), 910 (ins VReg_32:$src0, SSrc_32:$vsrc1), 911 "V_READLANE_B32 $vdst, $src0, $vsrc1", 912 [] 913>; 914 915def V_WRITELANE_B32 : VOP2 < 916 0x00000002, 917 (outs VReg_32:$vdst), 918 (ins SReg_32:$src0, SSrc_32:$vsrc1), 919 "V_WRITELANE_B32 $vdst, $src0, $vsrc1", 920 [] 921>; 922 923let isCommutable = 1 in { 924defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 925 [(set f32:$dst, (fadd f32:$src0, f32:$src1))] 926>; 927 928defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 929 [(set f32:$dst, (fsub f32:$src0, f32:$src1))] 930>; 931defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 932} // End isCommutable = 1 933 934defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 935 936let isCommutable = 1 in { 937 938defm V_MUL_LEGACY_F32 : VOP2_32 < 939 0x00000007, "V_MUL_LEGACY_F32", 940 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] 941>; 942 943defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 944 [(set f32:$dst, (fmul f32:$src0, f32:$src1))] 945>; 946 947 948defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", 949 [(set i32:$dst, (mul I24:$src0, I24:$src1))] 950>; 951//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 952defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", 953 [(set i32:$dst, (mul U24:$src0, U24:$src1))] 954>; 955//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 956 957 958defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 959 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] 960>; 961 962defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 963 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] 964>; 965 966defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 967defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 968defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", []>; 969defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>; 970defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>; 971defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>; 972 973defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", []>; 974defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 975 976defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", []>; 977defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 978 979let hasPostISelHook = 1 in { 980 981defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", []>; 982 983} 984defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 985 986defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", []>; 987defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", []>; 988defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", []>; 989 990} // End isCommutable = 1 991 992defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", 993 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>; 994defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 995defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 996defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 997//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 998defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 999defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 1000 1001let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 1002// No patterns so that the scalar instructions are always selected. 1003// The scalar versions will be replaced with vector when needed later. 1004defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", [], VSrc_32>; 1005defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", [], VSrc_32>; 1006defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32, 1007 "V_SUB_I32">; 1008 1009let Uses = [VCC] in { // Carry-in comes from VCC 1010defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", [], VReg_32>; 1011defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", [], VReg_32>; 1012defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32, 1013 "V_SUBB_U32">; 1014} // End Uses = [VCC] 1015} // End isCommutable = 1, Defs = [VCC] 1016 1017defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 1018////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 1019////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 1020////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 1021defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 1022 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] 1023>; 1024////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 1025////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 1026def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 1027def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 1028def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 1029def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 1030def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 1031def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 1032def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 1033def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 1034def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 1035def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 1036def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 1037def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 1038////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 1039////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 1040////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 1041////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 1042//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 1043 1044let neverHasSideEffects = 1 in { 1045 1046def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 1047def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 1048def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", 1049 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))] 1050>; 1051def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", 1052 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))] 1053>; 1054 1055} // End neverHasSideEffects 1056def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 1057def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 1058def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 1059def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 1060 1061let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in { 1062def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", 1063 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>; 1064def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", 1065 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>; 1066} 1067 1068def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", 1069 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>; 1070defm : BFIPatterns <V_BFI_B32>; 1071def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", 1072 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))] 1073>; 1074def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", 1075 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 1076>; 1077//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 1078def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 1079def : ROTRPattern <V_ALIGNBIT_B32>; 1080 1081def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 1082def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 1083////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 1084////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 1085////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 1086////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 1087////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 1088////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 1089////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 1090////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 1091////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 1092//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 1093//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 1094//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 1095def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 1096////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 1097def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 1098def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 1099 1100def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64", 1101 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1102>; 1103def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64", 1104 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1105>; 1106def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64", 1107 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1108>; 1109 1110let isCommutable = 1 in { 1111 1112def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 1113def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 1114def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 1115def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 1116 1117} // isCommutable = 1 1118 1119def : Pat < 1120 (fadd f64:$src0, f64:$src1), 1121 (V_ADD_F64 $src0, $src1, (i64 0)) 1122>; 1123 1124def : Pat < 1125 (fmul f64:$src0, f64:$src1), 1126 (V_MUL_F64 $src0, $src1, (i64 0)) 1127>; 1128 1129def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 1130 1131let isCommutable = 1 in { 1132 1133def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 1134def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 1135def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 1136def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 1137 1138} // isCommutable = 1 1139 1140def : Pat < 1141 (mul i32:$src0, i32:$src1), 1142 (V_MUL_LO_I32 $src0, $src1, (i32 0)) 1143>; 1144 1145def : Pat < 1146 (mulhu i32:$src0, i32:$src1), 1147 (V_MUL_HI_U32 $src0, $src1, (i32 0)) 1148>; 1149 1150def : Pat < 1151 (mulhs i32:$src0, i32:$src1), 1152 (V_MUL_HI_I32 $src0, $src1, (i32 0)) 1153>; 1154 1155def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1156def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1157def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1158def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1159//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1160//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1161//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1162def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1163 1164let Defs = [SCC] in { // Carry out goes to SCC 1165let isCommutable = 1 in { 1166def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 1167def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", 1168 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] 1169>; 1170} // End isCommutable = 1 1171 1172def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 1173def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", 1174 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] 1175>; 1176 1177let Uses = [SCC] in { // Carry in comes from SCC 1178let isCommutable = 1 in { 1179def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", 1180 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 1181} // End isCommutable = 1 1182 1183def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", 1184 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 1185} // End Uses = [SCC] 1186} // End Defs = [SCC] 1187 1188def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", 1189 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] 1190>; 1191def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", 1192 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] 1193>; 1194def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", 1195 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] 1196>; 1197def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", 1198 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] 1199>; 1200 1201def S_CSELECT_B32 : SOP2 < 1202 0x0000000a, (outs SReg_32:$dst), 1203 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1204 [] 1205>; 1206 1207def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1208 1209def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", 1210 [(set i32:$dst, (and i32:$src0, i32:$src1))] 1211>; 1212 1213def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1214 [(set i64:$dst, (and i64:$src0, i64:$src1))] 1215>; 1216 1217def : Pat < 1218 (i1 (and i1:$src0, i1:$src1)), 1219 (S_AND_B64 $src0, $src1) 1220>; 1221 1222def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", 1223 [(set i32:$dst, (or i32:$src0, i32:$src1))] 1224>; 1225 1226def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", 1227 [(set i64:$dst, (or i64:$src0, i64:$src1))] 1228>; 1229 1230def : Pat < 1231 (i1 (or i1:$src0, i1:$src1)), 1232 (S_OR_B64 $src0, $src1) 1233>; 1234 1235def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", 1236 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 1237>; 1238 1239def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", 1240 [(set i1:$dst, (xor i1:$src0, i1:$src1))] 1241>; 1242def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1243def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1244def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1245def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1246def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1247def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1248def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1249def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1250def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1251def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1252 1253// Use added complexity so these patterns are preferred to the VALU patterns. 1254let AddedComplexity = 1 in { 1255 1256def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", 1257 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 1258>; 1259def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64", 1260 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1261>; 1262def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", 1263 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 1264>; 1265def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64", 1266 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1267>; 1268def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", 1269 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 1270>; 1271def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64", 1272 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1273>; 1274 1275} // End AddedComplexity = 1 1276 1277def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1278def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1279def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1280def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1281def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1282def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1283def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1284//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1285def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1286 1287let isCodeGenOnly = 1, isPseudo = 1 in { 1288 1289def LOAD_CONST : AMDGPUShaderInst < 1290 (outs GPRF32:$dst), 1291 (ins i32imm:$src), 1292 "LOAD_CONST $dst, $src", 1293 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1294>; 1295 1296// SI pseudo instructions. These are used by the CFG structurizer pass 1297// and should be lowered to ISA instructions prior to codegen. 1298 1299let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1300 Uses = [EXEC], Defs = [EXEC] in { 1301 1302let isBranch = 1, isTerminator = 1 in { 1303 1304def SI_IF : InstSI < 1305 (outs SReg_64:$dst), 1306 (ins SReg_64:$vcc, brtarget:$target), 1307 "SI_IF $dst, $vcc, $target", 1308 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1309>; 1310 1311def SI_ELSE : InstSI < 1312 (outs SReg_64:$dst), 1313 (ins SReg_64:$src, brtarget:$target), 1314 "SI_ELSE $dst, $src, $target", 1315 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> { 1316 1317 let Constraints = "$src = $dst"; 1318} 1319 1320def SI_LOOP : InstSI < 1321 (outs), 1322 (ins SReg_64:$saved, brtarget:$target), 1323 "SI_LOOP $saved, $target", 1324 [(int_SI_loop i64:$saved, bb:$target)] 1325>; 1326 1327} // end isBranch = 1, isTerminator = 1 1328 1329def SI_BREAK : InstSI < 1330 (outs SReg_64:$dst), 1331 (ins SReg_64:$src), 1332 "SI_ELSE $dst, $src", 1333 [(set i64:$dst, (int_SI_break i64:$src))] 1334>; 1335 1336def SI_IF_BREAK : InstSI < 1337 (outs SReg_64:$dst), 1338 (ins SReg_64:$vcc, SReg_64:$src), 1339 "SI_IF_BREAK $dst, $vcc, $src", 1340 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1341>; 1342 1343def SI_ELSE_BREAK : InstSI < 1344 (outs SReg_64:$dst), 1345 (ins SReg_64:$src0, SReg_64:$src1), 1346 "SI_ELSE_BREAK $dst, $src0, $src1", 1347 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1348>; 1349 1350def SI_END_CF : InstSI < 1351 (outs), 1352 (ins SReg_64:$saved), 1353 "SI_END_CF $saved", 1354 [(int_SI_end_cf i64:$saved)] 1355>; 1356 1357def SI_KILL : InstSI < 1358 (outs), 1359 (ins VSrc_32:$src), 1360 "SI_KILL $src", 1361 [(int_AMDGPU_kill f32:$src)] 1362>; 1363 1364} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1365 // Uses = [EXEC], Defs = [EXEC] 1366 1367let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1368 1369//defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>; 1370 1371let UseNamedOperandTable = 1 in { 1372 1373def SI_RegisterLoad : AMDGPUShaderInst < 1374 (outs VReg_32:$dst, SReg_64:$temp), 1375 (ins FRAMEri32:$addr, i32imm:$chan), 1376 "", [] 1377> { 1378 let isRegisterLoad = 1; 1379 let mayLoad = 1; 1380} 1381 1382class SIRegStore<dag outs> : AMDGPUShaderInst < 1383 outs, 1384 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan), 1385 "", [] 1386> { 1387 let isRegisterStore = 1; 1388 let mayStore = 1; 1389} 1390 1391let usesCustomInserter = 1 in { 1392def SI_RegisterStorePseudo : SIRegStore<(outs)>; 1393} // End usesCustomInserter = 1 1394def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>; 1395 1396 1397} // End UseNamedOperandTable = 1 1398 1399def SI_INDIRECT_SRC : InstSI < 1400 (outs VReg_32:$dst, SReg_64:$temp), 1401 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1402 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1403 [] 1404>; 1405 1406class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1407 (outs rc:$dst, SReg_64:$temp), 1408 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1409 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1410 [] 1411> { 1412 let Constraints = "$src = $dst"; 1413} 1414 1415def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>; 1416def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1417def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1418def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1419def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1420 1421} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1422 1423let usesCustomInserter = 1 in { 1424 1425// This pseudo instruction takes a pointer as input and outputs a resource 1426// constant that can be used with the ADDR64 MUBUF instructions. 1427def SI_ADDR64_RSRC : InstSI < 1428 (outs SReg_128:$srsrc), 1429 (ins SReg_64:$ptr), 1430 "", [] 1431>; 1432 1433def V_SUB_F64 : InstSI < 1434 (outs VReg_64:$dst), 1435 (ins VReg_64:$src0, VReg_64:$src1), 1436 "V_SUB_F64 $dst, $src0, $src1", 1437 [] 1438>; 1439 1440} // end usesCustomInserter 1441 1442} // end IsCodeGenOnly, isPseudo 1443 1444def : Pat< 1445 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 1446 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) 1447>; 1448 1449def : Pat < 1450 (int_AMDGPU_kilp), 1451 (SI_KILL 0xbf800000) 1452>; 1453 1454/* int_SI_vs_load_input */ 1455def : Pat< 1456 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr), 1457 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0) 1458>; 1459 1460/* int_SI_export */ 1461def : Pat < 1462 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1463 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 1464 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1465 $src0, $src1, $src2, $src3) 1466>; 1467 1468def : Pat < 1469 (f64 (fsub f64:$src0, f64:$src1)), 1470 (V_SUB_F64 $src0, $src1) 1471>; 1472 1473/********** ======================= **********/ 1474/********** Image sampling patterns **********/ 1475/********** ======================= **********/ 1476 1477/* SIsample for simple 1D texture lookup */ 1478def : Pat < 1479 (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm), 1480 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1481>; 1482 1483class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1484 (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm), 1485 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1486>; 1487 1488class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1489 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT), 1490 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1491>; 1492 1493class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1494 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY), 1495 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1496>; 1497 1498class SampleShadowPattern<SDNode name, MIMG opcode, 1499 ValueType vt> : Pat < 1500 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW), 1501 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1502>; 1503 1504class SampleShadowArrayPattern<SDNode name, MIMG opcode, 1505 ValueType vt> : Pat < 1506 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY), 1507 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1508>; 1509 1510/* SIsample* for texture lookups consuming more address parameters */ 1511multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 1512 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 1513MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 1514 def : SamplePattern <SIsample, sample, addr_type>; 1515 def : SampleRectPattern <SIsample, sample, addr_type>; 1516 def : SampleArrayPattern <SIsample, sample, addr_type>; 1517 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 1518 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 1519 1520 def : SamplePattern <SIsamplel, sample_l, addr_type>; 1521 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 1522 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 1523 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 1524 1525 def : SamplePattern <SIsampleb, sample_b, addr_type>; 1526 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 1527 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 1528 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 1529 1530 def : SamplePattern <SIsampled, sample_d, addr_type>; 1531 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 1532 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 1533 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 1534} 1535 1536defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 1537 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 1538 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 1539 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 1540 v2i32>; 1541defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 1542 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 1543 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 1544 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 1545 v4i32>; 1546defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 1547 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 1548 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 1549 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 1550 v8i32>; 1551defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 1552 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 1553 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 1554 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 1555 v16i32>; 1556 1557/* int_SI_imageload for texture fetches consuming varying address parameters */ 1558class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1559 (name addr_type:$addr, v32i8:$rsrc, imm), 1560 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1561>; 1562 1563class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1564 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 1565 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1566>; 1567 1568class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1569 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA), 1570 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1571>; 1572 1573class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1574 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA), 1575 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1576>; 1577 1578multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> { 1579 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>; 1580 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>; 1581} 1582 1583multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> { 1584 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>; 1585 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>; 1586} 1587 1588defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>; 1589defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>; 1590 1591defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>; 1592defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>; 1593 1594/* Image resource information */ 1595def : Pat < 1596 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 1597 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1598>; 1599 1600def : Pat < 1601 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 1602 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1603>; 1604 1605def : Pat < 1606 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA), 1607 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1608>; 1609 1610/********** ============================================ **********/ 1611/********** Extraction, Insertion, Building and Casting **********/ 1612/********** ============================================ **********/ 1613 1614foreach Index = 0-2 in { 1615 def Extract_Element_v2i32_#Index : Extract_Element < 1616 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1617 >; 1618 def Insert_Element_v2i32_#Index : Insert_Element < 1619 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1620 >; 1621 1622 def Extract_Element_v2f32_#Index : Extract_Element < 1623 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1624 >; 1625 def Insert_Element_v2f32_#Index : Insert_Element < 1626 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1627 >; 1628} 1629 1630foreach Index = 0-3 in { 1631 def Extract_Element_v4i32_#Index : Extract_Element < 1632 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1633 >; 1634 def Insert_Element_v4i32_#Index : Insert_Element < 1635 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1636 >; 1637 1638 def Extract_Element_v4f32_#Index : Extract_Element < 1639 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1640 >; 1641 def Insert_Element_v4f32_#Index : Insert_Element < 1642 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1643 >; 1644} 1645 1646foreach Index = 0-7 in { 1647 def Extract_Element_v8i32_#Index : Extract_Element < 1648 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1649 >; 1650 def Insert_Element_v8i32_#Index : Insert_Element < 1651 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1652 >; 1653 1654 def Extract_Element_v8f32_#Index : Extract_Element < 1655 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1656 >; 1657 def Insert_Element_v8f32_#Index : Insert_Element < 1658 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1659 >; 1660} 1661 1662foreach Index = 0-15 in { 1663 def Extract_Element_v16i32_#Index : Extract_Element < 1664 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1665 >; 1666 def Insert_Element_v16i32_#Index : Insert_Element < 1667 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1668 >; 1669 1670 def Extract_Element_v16f32_#Index : Extract_Element < 1671 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1672 >; 1673 def Insert_Element_v16f32_#Index : Insert_Element < 1674 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1675 >; 1676} 1677 1678def : BitConvert <i32, f32, SReg_32>; 1679def : BitConvert <i32, f32, VReg_32>; 1680 1681def : BitConvert <f32, i32, SReg_32>; 1682def : BitConvert <f32, i32, VReg_32>; 1683 1684def : BitConvert <i64, f64, VReg_64>; 1685 1686def : BitConvert <f64, i64, VReg_64>; 1687 1688def : BitConvert <v2f32, v2i32, VReg_64>; 1689def : BitConvert <v2i32, v2f32, VReg_64>; 1690def : BitConvert <v2i32, i64, VReg_64>; 1691def : BitConvert <i64, v2i32, VReg_64>; 1692 1693def : BitConvert <v4f32, v4i32, VReg_128>; 1694def : BitConvert <v4i32, v4f32, VReg_128>; 1695def : BitConvert <v4i32, i128, VReg_128>; 1696def : BitConvert <i128, v4i32, VReg_128>; 1697 1698def : BitConvert <v8f32, v8i32, SReg_256>; 1699def : BitConvert <v8i32, v8f32, SReg_256>; 1700def : BitConvert <v8i32, v32i8, SReg_256>; 1701def : BitConvert <v32i8, v8i32, SReg_256>; 1702def : BitConvert <v8i32, v32i8, VReg_256>; 1703def : BitConvert <v8i32, v8f32, VReg_256>; 1704def : BitConvert <v8f32, v8i32, VReg_256>; 1705def : BitConvert <v32i8, v8i32, VReg_256>; 1706 1707def : BitConvert <v16i32, v16f32, VReg_512>; 1708def : BitConvert <v16f32, v16i32, VReg_512>; 1709 1710/********** =================== **********/ 1711/********** Src & Dst modifiers **********/ 1712/********** =================== **********/ 1713 1714def : Pat < 1715 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1716 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1717 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1718>; 1719 1720/********** ================================ **********/ 1721/********** Floating point absolute/negative **********/ 1722/********** ================================ **********/ 1723 1724// Manipulate the sign bit directly, as e.g. using the source negation modifier 1725// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0, 1726// breaking the piglit *s-floatBitsToInt-neg* tests 1727 1728// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly 1729// removing these patterns 1730 1731def : Pat < 1732 (fneg (fabs f32:$src)), 1733 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */ 1734>; 1735 1736def : Pat < 1737 (fabs f32:$src), 1738 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */ 1739>; 1740 1741def : Pat < 1742 (fneg f32:$src), 1743 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */ 1744>; 1745 1746/********** ================== **********/ 1747/********** Immediate Patterns **********/ 1748/********** ================== **********/ 1749 1750def : Pat < 1751 (SGPRImm<(i32 imm)>:$imm), 1752 (S_MOV_B32 imm:$imm) 1753>; 1754 1755def : Pat < 1756 (SGPRImm<(f32 fpimm)>:$imm), 1757 (S_MOV_B32 fpimm:$imm) 1758>; 1759 1760def : Pat < 1761 (i32 imm:$imm), 1762 (V_MOV_B32_e32 imm:$imm) 1763>; 1764 1765def : Pat < 1766 (f32 fpimm:$imm), 1767 (V_MOV_B32_e32 fpimm:$imm) 1768>; 1769 1770def : Pat < 1771 (i1 imm:$imm), 1772 (S_MOV_B64 imm:$imm) 1773>; 1774 1775def : Pat < 1776 (i64 InlineImm<i64>:$imm), 1777 (S_MOV_B64 InlineImm<i64>:$imm) 1778>; 1779 1780// i64 immediates aren't supported in hardware, split it into two 32bit values 1781def : Pat < 1782 (i64 imm:$imm), 1783 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1784 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1785 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1786>; 1787 1788def : Pat < 1789 (f64 fpimm:$imm), 1790 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 1791 (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0), 1792 (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1) 1793>; 1794 1795/********** ===================== **********/ 1796/********** Interpolation Paterns **********/ 1797/********** ===================== **********/ 1798 1799def : Pat < 1800 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params), 1801 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params) 1802>; 1803 1804def : Pat < 1805 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij), 1806 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0), 1807 imm:$attr_chan, imm:$attr, i32:$params), 1808 (EXTRACT_SUBREG $ij, sub1), 1809 imm:$attr_chan, imm:$attr, $params) 1810>; 1811 1812/********** ================== **********/ 1813/********** Intrinsic Patterns **********/ 1814/********** ================== **********/ 1815 1816/* llvm.AMDGPU.pow */ 1817def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 1818 1819def : Pat < 1820 (int_AMDGPU_div f32:$src0, f32:$src1), 1821 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 1822>; 1823 1824def : Pat< 1825 (fdiv f32:$src0, f32:$src1), 1826 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) 1827>; 1828 1829def : Pat< 1830 (fdiv f64:$src0, f64:$src1), 1831 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) 1832>; 1833 1834def : Pat < 1835 (fcos f32:$src0), 1836 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1837>; 1838 1839def : Pat < 1840 (fsin f32:$src0), 1841 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1842>; 1843 1844def : Pat < 1845 (int_AMDGPU_cube v4f32:$src), 1846 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1847 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), 1848 (EXTRACT_SUBREG $src, sub1), 1849 (EXTRACT_SUBREG $src, sub2)), 1850 sub0), 1851 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), 1852 (EXTRACT_SUBREG $src, sub1), 1853 (EXTRACT_SUBREG $src, sub2)), 1854 sub1), 1855 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), 1856 (EXTRACT_SUBREG $src, sub1), 1857 (EXTRACT_SUBREG $src, sub2)), 1858 sub2), 1859 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), 1860 (EXTRACT_SUBREG $src, sub1), 1861 (EXTRACT_SUBREG $src, sub2)), 1862 sub3) 1863>; 1864 1865def : Pat < 1866 (i32 (sext i1:$src0)), 1867 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 1868>; 1869 1870class Ext32Pat <SDNode ext> : Pat < 1871 (i32 (ext i1:$src0)), 1872 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0) 1873>; 1874 1875def : Ext32Pat <zext>; 1876def : Ext32Pat <anyext>; 1877 1878// 1. Offset as 8bit DWORD immediate 1879def : Pat < 1880 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset), 1881 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset)) 1882>; 1883 1884// 2. Offset loaded in an 32bit SGPR 1885def : Pat < 1886 (SIload_constant i128:$sbase, imm:$offset), 1887 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) 1888>; 1889 1890// 3. Offset in an 32Bit VGPR 1891def : Pat < 1892 (SIload_constant i128:$sbase, i32:$voff), 1893 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0) 1894>; 1895 1896// The multiplication scales from [0,1] to the unsigned integer range 1897def : Pat < 1898 (AMDGPUurecip i32:$src0), 1899 (V_CVT_U32_F32_e32 1900 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 1901 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 1902>; 1903 1904def : Pat < 1905 (int_SI_tid), 1906 (V_MBCNT_HI_U32_B32_e32 0xffffffff, 1907 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0)) 1908>; 1909 1910/********** ================== **********/ 1911/********** VOP3 Patterns **********/ 1912/********** ================== **********/ 1913 1914def : Pat < 1915 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)), 1916 (V_MAD_F32 $src0, $src1, $src2) 1917>; 1918 1919/********** ======================= **********/ 1920/********** Load/Store Patterns **********/ 1921/********** ======================= **********/ 1922 1923multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> { 1924 def : Pat < 1925 (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))), 1926 (inst (i1 0), $ptr, (as_i16imm $offset)) 1927 >; 1928 1929 def : Pat < 1930 (frag i32:$src0), 1931 (vt (inst 0, $src0, 0)) 1932 >; 1933} 1934 1935defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>; 1936defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>; 1937defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>; 1938defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>; 1939defm : DSReadPat <DS_READ_B32, i32, local_load>; 1940defm : DSReadPat <DS_READ_B64, i64, local_load>; 1941 1942multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> { 1943 def : Pat < 1944 (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))), 1945 (inst (i1 0), $ptr, $value, (as_i16imm $offset)) 1946 >; 1947 1948 def : Pat < 1949 (frag vt:$src1, i32:$src0), 1950 (inst 0, $src0, $src1, 0) 1951 >; 1952} 1953 1954defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>; 1955defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>; 1956defm : DSWritePat <DS_WRITE_B32, i32, local_store>; 1957defm : DSWritePat <DS_WRITE_B64, i64, local_store>; 1958 1959def : Pat <(atomic_load_add_local i32:$ptr, i32:$val), 1960 (DS_ADD_U32_RTN 0, $ptr, $val, 0)>; 1961 1962def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val), 1963 (DS_SUB_U32_RTN 0, $ptr, $val, 0)>; 1964 1965/********** ================== **********/ 1966/********** SMRD Patterns **********/ 1967/********** ================== **********/ 1968 1969multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1970 1971 // 1. Offset as 8bit DWORD immediate 1972 def : Pat < 1973 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))), 1974 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset))) 1975 >; 1976 1977 // 2. Offset loaded in an 32bit SGPR 1978 def : Pat < 1979 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)), 1980 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset))) 1981 >; 1982 1983 // 3. No offset at all 1984 def : Pat < 1985 (constant_load i64:$sbase), 1986 (vt (Instr_IMM $sbase, 0)) 1987 >; 1988} 1989 1990defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1991defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1992defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>; 1993defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>; 1994defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, i128>; 1995defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>; 1996defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1997defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>; 1998defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>; 1999 2000//===----------------------------------------------------------------------===// 2001// MUBUF Patterns 2002//===----------------------------------------------------------------------===// 2003 2004multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 2005 PatFrag global_ld, PatFrag constant_ld> { 2006 def : Pat < 2007 (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))), 2008 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset)) 2009 >; 2010 2011 def : Pat < 2012 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), 2013 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 2014 >; 2015 2016 def : Pat < 2017 (vt (global_ld i64:$ptr)), 2018 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 2019 >; 2020 2021 def : Pat < 2022 (vt (global_ld (add i64:$ptr, i64:$offset))), 2023 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 2024 >; 2025 2026 def : Pat < 2027 (vt (constant_ld (add i64:$ptr, i64:$offset))), 2028 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 2029 >; 2030} 2031 2032defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, 2033 sextloadi8_global, sextloadi8_constant>; 2034defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, 2035 az_extloadi8_global, az_extloadi8_constant>; 2036defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, 2037 sextloadi16_global, sextloadi16_constant>; 2038defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, 2039 az_extloadi16_global, az_extloadi16_constant>; 2040defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, 2041 global_load, constant_load>; 2042defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 2043 global_load, constant_load>; 2044defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 2045 az_extloadi32_global, az_extloadi32_constant>; 2046defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, 2047 global_load, constant_load>; 2048defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, 2049 global_load, constant_load>; 2050 2051multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> { 2052 2053 def : Pat < 2054 (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)), 2055 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset)) 2056 >; 2057 2058 def : Pat < 2059 (st vt:$value, (add i64:$ptr, IMM12bit:$offset)), 2060 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 2061 >; 2062 2063 def : Pat < 2064 (st vt:$value, i64:$ptr), 2065 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 2066 >; 2067 2068 def : Pat < 2069 (st vt:$value, (add i64:$ptr, i64:$offset)), 2070 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0) 2071 >; 2072} 2073 2074defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>; 2075defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>; 2076defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>; 2077defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>; 2078defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>; 2079defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>; 2080 2081// BUFFER_LOAD_DWORD*, addr64=0 2082multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen, 2083 MUBUF bothen> { 2084 2085 def : Pat < 2086 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset, 2087 imm:$offset, 0, 0, imm:$glc, imm:$slc, 2088 imm:$tfe)), 2089 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), 2090 (as_i1imm $slc), (as_i1imm $tfe)) 2091 >; 2092 2093 def : Pat < 2094 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset, 2095 imm, 1, 0, imm:$glc, imm:$slc, 2096 imm:$tfe)), 2097 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc), 2098 (as_i1imm $tfe)) 2099 >; 2100 2101 def : Pat < 2102 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset, 2103 imm:$offset, 0, 1, imm:$glc, imm:$slc, 2104 imm:$tfe)), 2105 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), 2106 (as_i1imm $slc), (as_i1imm $tfe)) 2107 >; 2108 2109 def : Pat < 2110 (vt (int_SI_buffer_load_dword i128:$rsrc, v2i32:$vaddr, i32:$soffset, 2111 imm, 1, 1, imm:$glc, imm:$slc, 2112 imm:$tfe)), 2113 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc), 2114 (as_i1imm $tfe)) 2115 >; 2116} 2117 2118defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN, 2119 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>; 2120defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN, 2121 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>; 2122defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN, 2123 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>; 2124 2125//===----------------------------------------------------------------------===// 2126// MTBUF Patterns 2127//===----------------------------------------------------------------------===// 2128 2129// TBUFFER_STORE_FORMAT_*, addr64=0 2130class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 2131 (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 2132 i32:$soffset, imm:$inst_offset, imm:$dfmt, 2133 imm:$nfmt, imm:$offen, imm:$idxen, 2134 imm:$glc, imm:$slc, imm:$tfe), 2135 (opcode 2136 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 2137 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 2138 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 2139>; 2140 2141def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 2142def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 2143def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 2144def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 2145 2146let Predicates = [isCI] in { 2147 2148// Sea island new arithmetic instructinos 2149let neverHasSideEffects = 1 in { 2150defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64", 2151 [(set f64:$dst, (ftrunc f64:$src0))] 2152>; 2153defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64", 2154 [(set f64:$dst, (fceil f64:$src0))] 2155>; 2156defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64", 2157 [(set f64:$dst, (ffloor f64:$src0))] 2158>; 2159 2160defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64", []>; 2161 2162def V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>; 2163def V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>; 2164def V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>; 2165def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>; 2166 2167// XXX - Does this set VCC? 2168def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>; 2169} // End neverHasSideEffects = 1 2170 2171// Remaining instructions: 2172// FLAT_* 2173// S_CBRANCH_CDBGUSER 2174// S_CBRANCH_CDBGSYS 2175// S_CBRANCH_CDBGSYS_OR_USER 2176// S_CBRANCH_CDBGSYS_AND_USER 2177// S_DCACHE_INV_VOL 2178// V_EXP_LEGACY_F32 2179// V_LOG_LEGACY_F32 2180// DS_NOP 2181// DS_GWS_SEMA_RELEASE_ALL 2182// DS_WRAP_RTN_B32 2183// DS_CNDXCHG32_RTN_B64 2184// DS_WRITE_B96 2185// DS_WRITE_B128 2186// DS_CONDXCHG32_RTN_B128 2187// DS_READ_B96 2188// DS_READ_B128 2189// BUFFER_LOAD_DWORDX3 2190// BUFFER_STORE_DWORDX3 2191 2192} // End Predicates = [isCI] 2193 2194 2195/********** ====================== **********/ 2196/********** Indirect adressing **********/ 2197/********** ====================== **********/ 2198 2199multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> { 2200 2201 // 1. Extract with offset 2202 def : Pat< 2203 (vector_extract vt:$vec, (add i32:$idx, imm:$off)), 2204 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) 2205 >; 2206 2207 // 2. Extract without offset 2208 def : Pat< 2209 (vector_extract vt:$vec, i32:$idx), 2210 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) 2211 >; 2212 2213 // 3. Insert with offset 2214 def : Pat< 2215 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)), 2216 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) 2217 >; 2218 2219 // 4. Insert without offset 2220 def : Pat< 2221 (vector_insert vt:$vec, eltvt:$val, i32:$idx), 2222 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) 2223 >; 2224} 2225 2226defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>; 2227defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>; 2228defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>; 2229defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>; 2230 2231defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>; 2232defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>; 2233defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>; 2234defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>; 2235 2236/********** =============== **********/ 2237/********** Conditions **********/ 2238/********** =============== **********/ 2239 2240def : Pat< 2241 (i1 (setcc f32:$src0, f32:$src1, SETO)), 2242 (V_CMP_O_F32_e64 $src0, $src1) 2243>; 2244 2245def : Pat< 2246 (i1 (setcc f32:$src0, f32:$src1, SETUO)), 2247 (V_CMP_U_F32_e64 $src0, $src1) 2248>; 2249 2250//===----------------------------------------------------------------------===// 2251// Miscellaneous Patterns 2252//===----------------------------------------------------------------------===// 2253 2254def : Pat < 2255 (i64 (trunc i128:$x)), 2256 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2257 (i32 (EXTRACT_SUBREG $x, sub0)), sub0), 2258 (i32 (EXTRACT_SUBREG $x, sub1)), sub1) 2259>; 2260 2261def : Pat < 2262 (i32 (trunc i64:$a)), 2263 (EXTRACT_SUBREG $a, sub0) 2264>; 2265 2266def : Pat < 2267 (i1 (trunc i32:$a)), 2268 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1) 2269>; 2270 2271// V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector 2272// case, the sgpr-copies pass will fix this to use the vector version. 2273def : Pat < 2274 (i32 (addc i32:$src0, i32:$src1)), 2275 (S_ADD_I32 $src0, $src1) 2276>; 2277 2278//============================================================================// 2279// Miscellaneous Optimization Patterns 2280//============================================================================// 2281 2282def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>; 2283 2284} // End isSI predicate 2285