SIInstructions.td revision 3e38856f04a01651819c6bc16fac4434a5d2b4c6
1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def isSI : Predicate<"Subtarget.getGeneration() " 26 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; 27 28def WAIT_FLAG : InstFlag<"printWaitFlag">; 29 30let Predicates = [isSI] in { 31 32let neverHasSideEffects = 1 in { 33 34let isMoveImm = 1 in { 35def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 36def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 37def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 38def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 39} // End isMoveImm = 1 40 41def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 42def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 43def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 44def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 45def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 46def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 47} // End neverHasSideEffects = 1 48 49////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 50////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 51////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 52////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 53////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 54////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 55////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 56////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 57//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 58//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 59def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 60//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 61//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 62//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 63////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 64////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 65////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 66////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 67def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 68def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 69def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 70def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 71 72let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 73 74def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 75def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 76def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 77def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 78def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 79def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 80def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 81def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 82 83} // End hasSideEffects = 1 84 85def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 86def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 87def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 88def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 89def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 90def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 91//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 92def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 93def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 94def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 95def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 96def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 97 98/* 99This instruction is disabled for now until we can figure out how to teach 100the instruction selector to correctly use the S_CMP* vs V_CMP* 101instructions. 102 103When this instruction is enabled the code generator sometimes produces this 104invalid sequence: 105 106SCC = S_CMPK_EQ_I32 SGPR0, imm 107VCC = COPY SCC 108VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 109 110def S_CMPK_EQ_I32 : SOPK < 111 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 112 "S_CMPK_EQ_I32", 113 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 114>; 115*/ 116 117let isCompare = 1 in { 118def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 119def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 120def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 121def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 122def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 123def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 124def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 125def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 126def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 127def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 128def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 129} // End isCompare = 1 130 131let Defs = [SCC], isCommutable = 1 in { 132 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 133 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 134} 135 136//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 137def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 138def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 139def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 140//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 141//def EXP : EXP_ <0x00000000, "EXP", []>; 142 143let isCompare = 1 in { 144 145defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 146defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_LT>; 147defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_EQ>; 148defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_LE>; 149defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_GT>; 150defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", f32, COND_NE>; 151defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_GE>; 152defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32">; 153defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32">; 154defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 155defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 156defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 157defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 158defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_NE>; 159defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 160defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 161 162let hasSideEffects = 1, Defs = [EXEC] in { 163 164defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 165defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 166defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 167defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 168defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 169defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 170defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 171defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 172defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 173defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 174defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 175defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 176defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 177defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 178defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 179defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 180 181} // End hasSideEffects = 1, Defs = [EXEC] 182 183defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 184defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_LT>; 185defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_EQ>; 186defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_LE>; 187defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_GT>; 188defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 189defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_GE>; 190defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64">; 191defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64">; 192defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 193defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 194defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 195defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 196defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_NE>; 197defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 198defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 199 200let hasSideEffects = 1, Defs = [EXEC] in { 201 202defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 203defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 204defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 205defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 206defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 207defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 208defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 209defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 210defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 211defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 212defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 213defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 214defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 215defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 216defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 217defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 218 219} // End hasSideEffects = 1, Defs = [EXEC] 220 221defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 222defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 223defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 224defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 225defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 226defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 227defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 228defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 229defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 230defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 231defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 232defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 233defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 234defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 235defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 236defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 237 238let hasSideEffects = 1, Defs = [EXEC] in { 239 240defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 241defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 242defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 243defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 244defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 245defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 246defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 247defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 248defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 249defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 250defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 251defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 252defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 253defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 254defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 255defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 256 257} // End hasSideEffects = 1, Defs = [EXEC] 258 259defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 260defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 261defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 262defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 263defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 264defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 265defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 266defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 267defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 268defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 269defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 270defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 271defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 272defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 273defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 274defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 275 276let hasSideEffects = 1, Defs = [EXEC] in { 277 278defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 279defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 280defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 281defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 282defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 283defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 284defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 285defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 286defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 287defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 288defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 289defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 290defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 291defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 292defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 293defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 294 295} // End hasSideEffects = 1, Defs = [EXEC] 296 297defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 298defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_LT>; 299defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 300defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_LE>; 301defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_GT>; 302defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 303defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_GE>; 304defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 305 306let hasSideEffects = 1, Defs = [EXEC] in { 307 308defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 309defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 310defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 311defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 312defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 313defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 314defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 315defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 316 317} // End hasSideEffects = 1, Defs = [EXEC] 318 319defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 320defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64">; 321defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64">; 322defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64">; 323defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64">; 324defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64">; 325defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64">; 326defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 327 328let hasSideEffects = 1, Defs = [EXEC] in { 329 330defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 331defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 332defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 333defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 334defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 335defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 336defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 337defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 338 339} // End hasSideEffects = 1, Defs = [EXEC] 340 341defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 342defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32">; 343defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32">; 344defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32">; 345defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32">; 346defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32">; 347defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32">; 348defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 349 350let hasSideEffects = 1, Defs = [EXEC] in { 351 352defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 353defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 354defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 355defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 356defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 357defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 358defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 359defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 360 361} // End hasSideEffects = 1, Defs = [EXEC] 362 363defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 364defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64">; 365defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64">; 366defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64">; 367defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64">; 368defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64">; 369defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64">; 370defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 371 372let hasSideEffects = 1, Defs = [EXEC] in { 373 374defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 375defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 376defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 377defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 378defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 379defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 380defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 381defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 382 383} // End hasSideEffects = 1, Defs = [EXEC] 384 385defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 386 387let hasSideEffects = 1, Defs = [EXEC] in { 388defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 389} // End hasSideEffects = 1, Defs = [EXEC] 390 391defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 392 393let hasSideEffects = 1, Defs = [EXEC] in { 394defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 395} // End hasSideEffects = 1, Defs = [EXEC] 396 397} // End isCompare = 1 398 399def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>; 400def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>; 401def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; 402def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>; 403def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>; 404def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>; 405def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>; 406def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>; 407def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>; 408def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; 409 410//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 411//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 412//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 413defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 414//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 415//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 416//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 417//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 418defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; 419defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>; 420defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>; 421defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>; 422defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 423defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 424defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 425 426def BUFFER_STORE_BYTE : MUBUF_Store_Helper < 427 0x00000018, "BUFFER_STORE_BYTE", VReg_32 428>; 429 430def BUFFER_STORE_SHORT : MUBUF_Store_Helper < 431 0x0000001a, "BUFFER_STORE_SHORT", VReg_32 432>; 433 434def BUFFER_STORE_DWORD : MUBUF_Store_Helper < 435 0x0000001c, "BUFFER_STORE_DWORD", VReg_32 436>; 437 438def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 439 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64 440>; 441 442def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 443 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128 444>; 445//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 446//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 447//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 448//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 449//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 450//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 451//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 452//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 453//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 454//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 455//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 456//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 457//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 458//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 459//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 460//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 461//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 462//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 463//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 464//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 465//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 466//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 467//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 468//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 469//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 470//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 471//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 472//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 473//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 474//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 475//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 476//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 477//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 478//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 479//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 480//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 481//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 482//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 483//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 484def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 485def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; 486def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; 487def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; 488def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; 489 490let mayLoad = 1 in { 491 492defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SReg_32>; 493defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 494defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 495defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 496defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 497 498defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 499 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SReg_32 500>; 501 502defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 503 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 504>; 505 506defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 507 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 508>; 509 510defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 511 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 512>; 513 514defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 515 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 516>; 517 518} // mayLoad = 1 519 520//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 521//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 522defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">; 523defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">; 524//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 525//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 526//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 527//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 528//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 529//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 530//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 531//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 532defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">; 533//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 534//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 535//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 536//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 537//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 538//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 539//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 540//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 541//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 542//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 543//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 544//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 545//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 546//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 547//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 548//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 549//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 550defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; 551//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 552defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; 553//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 554defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; 555defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; 556//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 557//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 558defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; 559//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 560defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; 561//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 562defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; 563defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; 564//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 565//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 566//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 567//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 568//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 569//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 570//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 571//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 572//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 573//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 574//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 575//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 576//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 577//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 578//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 579//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 580//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 581//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 582//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 583//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 584//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 585//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 586//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 587//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 588//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 589//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 590//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 591//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 592//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 593//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 594//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 595//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 596//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 597//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 598//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 599//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 600//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 601//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 602//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 603//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 604//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 605//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 606//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 607//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 608//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 609//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 610//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 611//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 612//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 613//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 614//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 615//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 616//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 617//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 618 619 620let neverHasSideEffects = 1, isMoveImm = 1 in { 621defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 622} // End neverHasSideEffects = 1, isMoveImm = 1 623 624defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 625defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", 626 [(set i32:$dst, (fp_to_sint f64:$src0))] 627>; 628defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32", 629 [(set f64:$dst, (sint_to_fp i32:$src0))] 630>; 631defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 632 [(set f32:$dst, (sint_to_fp i32:$src0))] 633>; 634defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", 635 [(set f32:$dst, (uint_to_fp i32:$src0))] 636>; 637defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", 638 [(set i32:$dst, (fp_to_uint f32:$src0))] 639>; 640defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 641 [(set i32:$dst, (fp_to_sint f32:$src0))] 642>; 643defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 644////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 645//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 646//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 647//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 648//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 649defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64", 650 [(set f32:$dst, (fround f64:$src0))] 651>; 652defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32", 653 [(set f64:$dst, (fextend f32:$src0))] 654>; 655//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 656//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 657//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 658//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 659//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 660//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 661defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 662 [(set f32:$dst, (AMDGPUfract f32:$src0))] 663>; 664defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", 665 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] 666>; 667defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 668 [(set f32:$dst, (fceil f32:$src0))] 669>; 670defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 671 [(set f32:$dst, (frint f32:$src0))] 672>; 673defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 674 [(set f32:$dst, (ffloor f32:$src0))] 675>; 676defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 677 [(set f32:$dst, (fexp2 f32:$src0))] 678>; 679defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 680defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 681 [(set f32:$dst, (flog2 f32:$src0))] 682>; 683defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 684defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 685defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 686 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 687>; 688defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 689defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 690defm V_RSQ_LEGACY_F32 : VOP1_32 < 691 0x0000002d, "V_RSQ_LEGACY_F32", 692 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] 693>; 694defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 695defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", 696 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))] 697>; 698defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 699defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 700defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 701defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", 702 [(set f32:$dst, (fsqrt f32:$src0))] 703>; 704defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", 705 [(set f64:$dst, (fsqrt f64:$src0))] 706>; 707defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 708defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 709defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 710defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 711defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 712defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 713defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 714//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 715defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 716defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 717//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 718defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 719//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 720defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 721defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 722defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 723 724def V_INTERP_P1_F32 : VINTRP < 725 0x00000000, 726 (outs VReg_32:$dst), 727 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 728 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 729 []> { 730 let DisableEncoding = "$m0"; 731} 732 733def V_INTERP_P2_F32 : VINTRP < 734 0x00000001, 735 (outs VReg_32:$dst), 736 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 737 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 738 []> { 739 740 let Constraints = "$src0 = $dst"; 741 let DisableEncoding = "$src0,$m0"; 742 743} 744 745def V_INTERP_MOV_F32 : VINTRP < 746 0x00000002, 747 (outs VReg_32:$dst), 748 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 749 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 750 []> { 751 let DisableEncoding = "$m0"; 752} 753 754//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 755 756let isTerminator = 1 in { 757 758def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 759 [(IL_retflag)]> { 760 let SIMM16 = 0; 761 let isBarrier = 1; 762 let hasCtrlDep = 1; 763} 764 765let isBranch = 1 in { 766def S_BRANCH : SOPP < 767 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 768 [(br bb:$target)]> { 769 let isBarrier = 1; 770} 771 772let DisableEncoding = "$scc" in { 773def S_CBRANCH_SCC0 : SOPP < 774 0x00000004, (ins brtarget:$target, SCCReg:$scc), 775 "S_CBRANCH_SCC0 $target", [] 776>; 777def S_CBRANCH_SCC1 : SOPP < 778 0x00000005, (ins brtarget:$target, SCCReg:$scc), 779 "S_CBRANCH_SCC1 $target", 780 [] 781>; 782} // End DisableEncoding = "$scc" 783 784def S_CBRANCH_VCCZ : SOPP < 785 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 786 "S_CBRANCH_VCCZ $target", 787 [] 788>; 789def S_CBRANCH_VCCNZ : SOPP < 790 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 791 "S_CBRANCH_VCCNZ $target", 792 [] 793>; 794 795let DisableEncoding = "$exec" in { 796def S_CBRANCH_EXECZ : SOPP < 797 0x00000008, (ins brtarget:$target, EXECReg:$exec), 798 "S_CBRANCH_EXECZ $target", 799 [] 800>; 801def S_CBRANCH_EXECNZ : SOPP < 802 0x00000009, (ins brtarget:$target, EXECReg:$exec), 803 "S_CBRANCH_EXECNZ $target", 804 [] 805>; 806} // End DisableEncoding = "$exec" 807 808 809} // End isBranch = 1 810} // End isTerminator = 1 811 812let hasSideEffects = 1 in { 813def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", 814 [(int_AMDGPU_barrier_local)] 815> { 816 let SIMM16 = 0; 817 let isBarrier = 1; 818 let hasCtrlDep = 1; 819 let mayLoad = 1; 820 let mayStore = 1; 821} 822 823def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16", 824 [] 825>; 826} // End hasSideEffects 827//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 828//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 829//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 830//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>; 831//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 832//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 833//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 834//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 835//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 836//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 837 838def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 839 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 840 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 841 [] 842>{ 843 let DisableEncoding = "$vcc"; 844} 845 846def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 847 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 848 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 849 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 850 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] 851>; 852 853//f32 pattern for V_CNDMASK_B32_e64 854def : Pat < 855 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 856 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 857>; 858 859def : Pat < 860 (i32 (trunc i64:$val)), 861 (EXTRACT_SUBREG $val, sub0) 862>; 863 864//use two V_CNDMASK_B32_e64 instructions for f64 865def : Pat < 866 (f64 (select i1:$src2, f64:$src1, f64:$src0)), 867 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 868 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0), 869 (EXTRACT_SUBREG $src1, sub0), 870 $src2), sub0), 871 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1), 872 (EXTRACT_SUBREG $src1, sub1), 873 $src2), sub1) 874>; 875 876defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 877defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 878 879let isCommutable = 1 in { 880defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 881 [(set f32:$dst, (fadd f32:$src0, f32:$src1))] 882>; 883 884defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 885 [(set f32:$dst, (fsub f32:$src0, f32:$src1))] 886>; 887defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 888} // End isCommutable = 1 889 890defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 891 892let isCommutable = 1 in { 893 894defm V_MUL_LEGACY_F32 : VOP2_32 < 895 0x00000007, "V_MUL_LEGACY_F32", 896 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] 897>; 898 899defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 900 [(set f32:$dst, (fmul f32:$src0, f32:$src1))] 901>; 902 903 904defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", 905 [(set i32:$dst, (mul I24:$src0, I24:$src1))] 906>; 907//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 908defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", 909 [(set i32:$dst, (mul U24:$src0, U24:$src1))] 910>; 911//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 912 913 914defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 915 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] 916>; 917 918defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 919 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] 920>; 921 922defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 923defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 924defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", 925 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] 926>; 927defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", 928 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] 929>; 930defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", 931 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] 932>; 933defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", 934 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] 935>; 936 937defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", 938 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 939>; 940defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 941 942defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", 943 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 944>; 945defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 946 947let hasPostISelHook = 1 in { 948 949defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 950 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 951>; 952 953} 954defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 955 956defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 957 [(set i32:$dst, (and i32:$src0, i32:$src1))] 958>; 959defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 960 [(set i32:$dst, (or i32:$src0, i32:$src1))] 961>; 962defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 963 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 964>; 965 966} // End isCommutable = 1 967 968defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 969defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 970defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 971defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 972//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 973defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 974defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 975 976let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 977// No patterns so that the scalar instructions are always selected. 978// The scalar versions will be replaced with vector when needed later. 979defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", []>; 980defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", []>; 981defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">; 982 983let Uses = [VCC] in { // Carry-in comes from VCC 984defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>; 985defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>; 986defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">; 987} // End Uses = [VCC] 988} // End isCommutable = 1, Defs = [VCC] 989 990defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 991////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 992////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 993////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 994defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 995 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] 996>; 997////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 998////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 999def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 1000def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 1001def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 1002def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 1003def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 1004def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 1005def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 1006def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 1007def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 1008def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 1009def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 1010def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 1011////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 1012////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 1013////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 1014////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 1015//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 1016 1017let neverHasSideEffects = 1 in { 1018 1019def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 1020def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 1021def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", 1022 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))] 1023>; 1024def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", 1025 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))] 1026>; 1027 1028} // End neverHasSideEffects 1029def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 1030def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 1031def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 1032def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 1033def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 1034def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 1035def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 1036defm : BFIPatterns <V_BFI_B32>; 1037def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", 1038 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))] 1039>; 1040def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", 1041 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 1042>; 1043//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 1044def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 1045def : ROTRPattern <V_ALIGNBIT_B32>; 1046 1047def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 1048def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 1049////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 1050////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 1051////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 1052////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 1053////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 1054////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 1055////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 1056////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 1057////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 1058//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 1059//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 1060//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 1061def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 1062////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 1063def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 1064def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 1065 1066def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64", 1067 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1068>; 1069def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64", 1070 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1071>; 1072def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64", 1073 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1074>; 1075 1076let isCommutable = 1 in { 1077 1078def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 1079def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 1080def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 1081def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 1082 1083} // isCommutable = 1 1084 1085def : Pat < 1086 (fadd f64:$src0, f64:$src1), 1087 (V_ADD_F64 $src0, $src1, (i64 0)) 1088>; 1089 1090def : Pat < 1091 (fmul f64:$src0, f64:$src1), 1092 (V_MUL_F64 $src0, $src1, (i64 0)) 1093>; 1094 1095def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 1096 1097let isCommutable = 1 in { 1098 1099def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 1100def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 1101def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 1102def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 1103 1104} // isCommutable = 1 1105 1106def : Pat < 1107 (mul i32:$src0, i32:$src1), 1108 (V_MUL_LO_I32 $src0, $src1, (i32 0)) 1109>; 1110 1111def : Pat < 1112 (mulhu i32:$src0, i32:$src1), 1113 (V_MUL_HI_U32 $src0, $src1, (i32 0)) 1114>; 1115 1116def : Pat < 1117 (mulhs i32:$src0, i32:$src1), 1118 (V_MUL_HI_I32 $src0, $src1, (i32 0)) 1119>; 1120 1121def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1122def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1123def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1124def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1125//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1126//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1127//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1128def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1129def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 1130def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 1131def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", 1132 [(set i32:$dst, (add i32:$src0, i32:$src1))] 1133>; 1134def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", 1135 [(set i32:$dst, (sub i32:$src0, i32:$src1))] 1136>; 1137 1138def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>; 1139def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>; 1140def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 1141def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 1142def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 1143def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 1144 1145def S_CSELECT_B32 : SOP2 < 1146 0x0000000a, (outs SReg_32:$dst), 1147 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1148 [] 1149>; 1150 1151def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1152 1153def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 1154 1155def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1156 [(set i64:$dst, (and i64:$src0, i64:$src1))] 1157>; 1158 1159def : Pat < 1160 (i1 (and i1:$src0, i1:$src1)), 1161 (S_AND_B64 $src0, $src1) 1162>; 1163 1164def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 1165def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 1166def : Pat < 1167 (i1 (or i1:$src0, i1:$src1)), 1168 (S_OR_B64 $src0, $src1) 1169>; 1170def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 1171def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", 1172 [(set i1:$dst, (xor i1:$src0, i1:$src1))] 1173>; 1174def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1175def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1176def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1177def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1178def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1179def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1180def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1181def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1182def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1183def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1184 1185// Use added complexity so these patterns are preferred to the VALU patterns. 1186let AddedComplexity = 1 in { 1187 1188def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", 1189 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 1190>; 1191def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64", 1192 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1193>; 1194def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", 1195 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 1196>; 1197def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64", 1198 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1199>; 1200def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", 1201 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 1202>; 1203def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64", 1204 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1205>; 1206 1207} // End AddedComplexity = 1 1208 1209def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1210def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1211def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1212def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1213def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1214def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1215def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1216//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1217def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1218 1219let isCodeGenOnly = 1, isPseudo = 1 in { 1220 1221def LOAD_CONST : AMDGPUShaderInst < 1222 (outs GPRF32:$dst), 1223 (ins i32imm:$src), 1224 "LOAD_CONST $dst, $src", 1225 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1226>; 1227 1228// SI pseudo instructions. These are used by the CFG structurizer pass 1229// and should be lowered to ISA instructions prior to codegen. 1230 1231let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1232 Uses = [EXEC], Defs = [EXEC] in { 1233 1234let isBranch = 1, isTerminator = 1 in { 1235 1236def SI_IF : InstSI < 1237 (outs SReg_64:$dst), 1238 (ins SReg_64:$vcc, brtarget:$target), 1239 "SI_IF $dst, $vcc, $target", 1240 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1241>; 1242 1243def SI_ELSE : InstSI < 1244 (outs SReg_64:$dst), 1245 (ins SReg_64:$src, brtarget:$target), 1246 "SI_ELSE $dst, $src, $target", 1247 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> { 1248 1249 let Constraints = "$src = $dst"; 1250} 1251 1252def SI_LOOP : InstSI < 1253 (outs), 1254 (ins SReg_64:$saved, brtarget:$target), 1255 "SI_LOOP $saved, $target", 1256 [(int_SI_loop i64:$saved, bb:$target)] 1257>; 1258 1259} // end isBranch = 1, isTerminator = 1 1260 1261def SI_BREAK : InstSI < 1262 (outs SReg_64:$dst), 1263 (ins SReg_64:$src), 1264 "SI_ELSE $dst, $src", 1265 [(set i64:$dst, (int_SI_break i64:$src))] 1266>; 1267 1268def SI_IF_BREAK : InstSI < 1269 (outs SReg_64:$dst), 1270 (ins SReg_64:$vcc, SReg_64:$src), 1271 "SI_IF_BREAK $dst, $vcc, $src", 1272 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1273>; 1274 1275def SI_ELSE_BREAK : InstSI < 1276 (outs SReg_64:$dst), 1277 (ins SReg_64:$src0, SReg_64:$src1), 1278 "SI_ELSE_BREAK $dst, $src0, $src1", 1279 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1280>; 1281 1282def SI_END_CF : InstSI < 1283 (outs), 1284 (ins SReg_64:$saved), 1285 "SI_END_CF $saved", 1286 [(int_SI_end_cf i64:$saved)] 1287>; 1288 1289def SI_KILL : InstSI < 1290 (outs), 1291 (ins VReg_32:$src), 1292 "SI_KIL $src", 1293 [(int_AMDGPU_kill f32:$src)] 1294>; 1295 1296} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1297 // Uses = [EXEC], Defs = [EXEC] 1298 1299let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1300 1301//defm SI_ : RegisterLoadStore <VReg_32, FRAMEri64, ADDRIndirect>; 1302 1303let UseNamedOperandTable = 1 in { 1304 1305def SI_RegisterLoad : AMDGPUShaderInst < 1306 (outs VReg_32:$dst, SReg_64:$temp), 1307 (ins FRAMEri64:$addr, i32imm:$chan), 1308 "", [] 1309> { 1310 let isRegisterLoad = 1; 1311 let mayLoad = 1; 1312} 1313 1314class SIRegStore<dag outs> : AMDGPUShaderInst < 1315 outs, 1316 (ins VReg_32:$val, FRAMEri64:$addr, i32imm:$chan), 1317 "", [] 1318> { 1319 let isRegisterStore = 1; 1320 let mayStore = 1; 1321} 1322 1323let usesCustomInserter = 1 in { 1324def SI_RegisterStorePseudo : SIRegStore<(outs)>; 1325} // End usesCustomInserter = 1 1326def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>; 1327 1328 1329} // End UseNamedOperandTable = 1 1330 1331def SI_INDIRECT_SRC : InstSI < 1332 (outs VReg_32:$dst, SReg_64:$temp), 1333 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1334 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1335 [] 1336>; 1337 1338class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1339 (outs rc:$dst, SReg_64:$temp), 1340 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1341 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1342 [] 1343> { 1344 let Constraints = "$src = $dst"; 1345} 1346 1347def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>; 1348def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1349def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1350def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1351def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1352 1353} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1354 1355let usesCustomInserter = 1 in { 1356 1357// This pseudo instruction takes a pointer as input and outputs a resource 1358// constant that can be used with the ADDR64 MUBUF instructions. 1359def SI_ADDR64_RSRC : InstSI < 1360 (outs SReg_128:$srsrc), 1361 (ins SReg_64:$ptr), 1362 "", [] 1363>; 1364 1365def V_SUB_F64 : InstSI < 1366 (outs VReg_64:$dst), 1367 (ins VReg_64:$src0, VReg_64:$src1), 1368 "V_SUB_F64 $dst, $src0, $src1", 1369 [] 1370>; 1371 1372} // end usesCustomInserter 1373 1374} // end IsCodeGenOnly, isPseudo 1375 1376def : Pat< 1377 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 1378 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) 1379>; 1380 1381def : Pat < 1382 (int_AMDGPU_kilp), 1383 (SI_KILL (V_MOV_B32_e32 0xbf800000)) 1384>; 1385 1386/* int_SI_vs_load_input */ 1387def : Pat< 1388 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr), 1389 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset) 1390>; 1391 1392/* int_SI_export */ 1393def : Pat < 1394 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1395 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 1396 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1397 $src0, $src1, $src2, $src3) 1398>; 1399 1400def : Pat < 1401 (f64 (fsub f64:$src0, f64:$src1)), 1402 (V_SUB_F64 $src0, $src1) 1403>; 1404 1405/********** ======================= **********/ 1406/********** Image sampling patterns **********/ 1407/********** ======================= **********/ 1408 1409/* SIsample for simple 1D texture lookup */ 1410def : Pat < 1411 (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm), 1412 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1413>; 1414 1415class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1416 (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm), 1417 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1418>; 1419 1420class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1421 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT), 1422 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1423>; 1424 1425class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1426 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY), 1427 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1428>; 1429 1430class SampleShadowPattern<SDNode name, MIMG opcode, 1431 ValueType vt> : Pat < 1432 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW), 1433 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1434>; 1435 1436class SampleShadowArrayPattern<SDNode name, MIMG opcode, 1437 ValueType vt> : Pat < 1438 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY), 1439 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1440>; 1441 1442/* SIsample* for texture lookups consuming more address parameters */ 1443multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 1444 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 1445MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 1446 def : SamplePattern <SIsample, sample, addr_type>; 1447 def : SampleRectPattern <SIsample, sample, addr_type>; 1448 def : SampleArrayPattern <SIsample, sample, addr_type>; 1449 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 1450 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 1451 1452 def : SamplePattern <SIsamplel, sample_l, addr_type>; 1453 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 1454 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 1455 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 1456 1457 def : SamplePattern <SIsampleb, sample_b, addr_type>; 1458 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 1459 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 1460 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 1461 1462 def : SamplePattern <SIsampled, sample_d, addr_type>; 1463 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 1464 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 1465 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 1466} 1467 1468defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 1469 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 1470 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 1471 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 1472 v2i32>; 1473defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 1474 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 1475 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 1476 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 1477 v4i32>; 1478defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 1479 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 1480 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 1481 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 1482 v8i32>; 1483defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 1484 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 1485 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 1486 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 1487 v16i32>; 1488 1489/* int_SI_imageload for texture fetches consuming varying address parameters */ 1490class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1491 (name addr_type:$addr, v32i8:$rsrc, imm), 1492 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1493>; 1494 1495class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1496 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 1497 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1498>; 1499 1500class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1501 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA), 1502 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1503>; 1504 1505class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1506 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA), 1507 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1508>; 1509 1510multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> { 1511 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>; 1512 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>; 1513} 1514 1515multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> { 1516 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>; 1517 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>; 1518} 1519 1520defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>; 1521defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>; 1522 1523defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>; 1524defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>; 1525 1526/* Image resource information */ 1527def : Pat < 1528 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 1529 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1530>; 1531 1532def : Pat < 1533 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 1534 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1535>; 1536 1537def : Pat < 1538 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA), 1539 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1540>; 1541 1542/********** ============================================ **********/ 1543/********** Extraction, Insertion, Building and Casting **********/ 1544/********** ============================================ **********/ 1545 1546foreach Index = 0-2 in { 1547 def Extract_Element_v2i32_#Index : Extract_Element < 1548 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1549 >; 1550 def Insert_Element_v2i32_#Index : Insert_Element < 1551 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1552 >; 1553 1554 def Extract_Element_v2f32_#Index : Extract_Element < 1555 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1556 >; 1557 def Insert_Element_v2f32_#Index : Insert_Element < 1558 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1559 >; 1560} 1561 1562foreach Index = 0-3 in { 1563 def Extract_Element_v4i32_#Index : Extract_Element < 1564 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1565 >; 1566 def Insert_Element_v4i32_#Index : Insert_Element < 1567 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1568 >; 1569 1570 def Extract_Element_v4f32_#Index : Extract_Element < 1571 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1572 >; 1573 def Insert_Element_v4f32_#Index : Insert_Element < 1574 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1575 >; 1576} 1577 1578foreach Index = 0-7 in { 1579 def Extract_Element_v8i32_#Index : Extract_Element < 1580 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1581 >; 1582 def Insert_Element_v8i32_#Index : Insert_Element < 1583 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1584 >; 1585 1586 def Extract_Element_v8f32_#Index : Extract_Element < 1587 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1588 >; 1589 def Insert_Element_v8f32_#Index : Insert_Element < 1590 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1591 >; 1592} 1593 1594foreach Index = 0-15 in { 1595 def Extract_Element_v16i32_#Index : Extract_Element < 1596 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1597 >; 1598 def Insert_Element_v16i32_#Index : Insert_Element < 1599 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1600 >; 1601 1602 def Extract_Element_v16f32_#Index : Extract_Element < 1603 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1604 >; 1605 def Insert_Element_v16f32_#Index : Insert_Element < 1606 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1607 >; 1608} 1609 1610def : BitConvert <i32, f32, SReg_32>; 1611def : BitConvert <i32, f32, VReg_32>; 1612 1613def : BitConvert <f32, i32, SReg_32>; 1614def : BitConvert <f32, i32, VReg_32>; 1615 1616def : BitConvert <i64, f64, VReg_64>; 1617 1618def : BitConvert <f64, i64, VReg_64>; 1619 1620def : BitConvert <v2f32, v2i32, VReg_64>; 1621def : BitConvert <v2i32, v2f32, VReg_64>; 1622def : BitConvert <v2i32, i64, VReg_64>; 1623 1624def : BitConvert <v4f32, v4i32, VReg_128>; 1625def : BitConvert <v4i32, v4f32, VReg_128>; 1626def : BitConvert <v4i32, i128, VReg_128>; 1627def : BitConvert <i128, v4i32, VReg_128>; 1628 1629def : BitConvert <v8i32, v32i8, SReg_256>; 1630def : BitConvert <v32i8, v8i32, SReg_256>; 1631def : BitConvert <v8i32, v32i8, VReg_256>; 1632def : BitConvert <v32i8, v8i32, VReg_256>; 1633 1634/********** =================== **********/ 1635/********** Src & Dst modifiers **********/ 1636/********** =================== **********/ 1637 1638def : Pat < 1639 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1640 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1641 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1642>; 1643 1644def : Pat < 1645 (fabs f32:$src), 1646 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1647 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1648>; 1649 1650def : Pat < 1651 (fneg f32:$src), 1652 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1653 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */) 1654>; 1655 1656/********** ================== **********/ 1657/********** Immediate Patterns **********/ 1658/********** ================== **********/ 1659 1660def : Pat < 1661 (SGPRImm<(i32 imm)>:$imm), 1662 (S_MOV_B32 imm:$imm) 1663>; 1664 1665def : Pat < 1666 (SGPRImm<(f32 fpimm)>:$imm), 1667 (S_MOV_B32 fpimm:$imm) 1668>; 1669 1670def : Pat < 1671 (i32 imm:$imm), 1672 (V_MOV_B32_e32 imm:$imm) 1673>; 1674 1675def : Pat < 1676 (f32 fpimm:$imm), 1677 (V_MOV_B32_e32 fpimm:$imm) 1678>; 1679 1680def : Pat < 1681 (i1 imm:$imm), 1682 (S_MOV_B64 imm:$imm) 1683>; 1684 1685def : Pat < 1686 (i64 InlineImm<i64>:$imm), 1687 (S_MOV_B64 InlineImm<i64>:$imm) 1688>; 1689 1690// i64 immediates aren't supported in hardware, split it into two 32bit values 1691def : Pat < 1692 (i64 imm:$imm), 1693 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1694 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1695 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1696>; 1697 1698def : Pat < 1699 (f64 fpimm:$imm), 1700 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 1701 (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0), 1702 (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1) 1703>; 1704 1705/********** ===================== **********/ 1706/********** Interpolation Paterns **********/ 1707/********** ===================== **********/ 1708 1709def : Pat < 1710 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params), 1711 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params) 1712>; 1713 1714def : Pat < 1715 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij), 1716 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0), 1717 imm:$attr_chan, imm:$attr, i32:$params), 1718 (EXTRACT_SUBREG $ij, sub1), 1719 imm:$attr_chan, imm:$attr, $params) 1720>; 1721 1722/********** ================== **********/ 1723/********** Intrinsic Patterns **********/ 1724/********** ================== **********/ 1725 1726/* llvm.AMDGPU.pow */ 1727def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 1728 1729def : Pat < 1730 (int_AMDGPU_div f32:$src0, f32:$src1), 1731 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 1732>; 1733 1734def : Pat< 1735 (fdiv f32:$src0, f32:$src1), 1736 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) 1737>; 1738 1739def : Pat< 1740 (fdiv f64:$src0, f64:$src1), 1741 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) 1742>; 1743 1744def : Pat < 1745 (fcos f32:$src0), 1746 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1747>; 1748 1749def : Pat < 1750 (fsin f32:$src0), 1751 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1752>; 1753 1754def : Pat < 1755 (int_AMDGPU_cube v4f32:$src), 1756 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1757 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), 1758 (EXTRACT_SUBREG $src, sub1), 1759 (EXTRACT_SUBREG $src, sub2)), 1760 sub0), 1761 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), 1762 (EXTRACT_SUBREG $src, sub1), 1763 (EXTRACT_SUBREG $src, sub2)), 1764 sub1), 1765 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), 1766 (EXTRACT_SUBREG $src, sub1), 1767 (EXTRACT_SUBREG $src, sub2)), 1768 sub2), 1769 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), 1770 (EXTRACT_SUBREG $src, sub1), 1771 (EXTRACT_SUBREG $src, sub2)), 1772 sub3) 1773>; 1774 1775def : Pat < 1776 (i32 (sext i1:$src0)), 1777 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 1778>; 1779 1780// 1. Offset as 8bit DWORD immediate 1781def : Pat < 1782 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset), 1783 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset) 1784>; 1785 1786// 2. Offset loaded in an 32bit SGPR 1787def : Pat < 1788 (SIload_constant i128:$sbase, imm:$offset), 1789 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) 1790>; 1791 1792// 3. Offset in an 32Bit VGPR 1793def : Pat < 1794 (SIload_constant i128:$sbase, i32:$voff), 1795 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff) 1796>; 1797 1798// The multiplication scales from [0,1] to the unsigned integer range 1799def : Pat < 1800 (AMDGPUurecip i32:$src0), 1801 (V_CVT_U32_F32_e32 1802 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 1803 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 1804>; 1805 1806def : Pat < 1807 (int_SI_tid), 1808 (V_MBCNT_HI_U32_B32_e32 0xffffffff, 1809 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0)) 1810>; 1811 1812/********** ================== **********/ 1813/********** VOP3 Patterns **********/ 1814/********** ================== **********/ 1815 1816def : Pat < 1817 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)), 1818 (V_MAD_F32 $src0, $src1, $src2) 1819>; 1820 1821/********** ======================= **********/ 1822/********** Load/Store Patterns **********/ 1823/********** ======================= **********/ 1824 1825class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat < 1826 (frag i32:$src0), 1827 (vt (inst 0, $src0, $src0, $src0, 0, 0)) 1828>; 1829 1830def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>; 1831def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>; 1832def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>; 1833def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>; 1834def : DSReadPat <DS_READ_B32, i32, local_load>; 1835def : Pat < 1836 (local_load i32:$src0), 1837 (i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0)) 1838>; 1839 1840class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat < 1841 (frag i32:$src1, i32:$src0), 1842 (inst 0, $src0, $src1, $src1, 0, 0) 1843>; 1844 1845def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>; 1846def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>; 1847def : DSWritePat <DS_WRITE_B32, i32, local_store>; 1848 1849def : Pat <(atomic_load_add_local i32:$ptr, i32:$val), 1850 (DS_ADD_U32_RTN 0, $ptr, $val, 0, 0)>; 1851 1852def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val), 1853 (DS_SUB_U32_RTN 0, $ptr, $val, 0, 0)>; 1854 1855/********** ================== **********/ 1856/********** SMRD Patterns **********/ 1857/********** ================== **********/ 1858 1859multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1860 1861 // 1. Offset as 8bit DWORD immediate 1862 def : Pat < 1863 (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)), 1864 (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset)) 1865 >; 1866 1867 // 2. Offset loaded in an 32bit SGPR 1868 def : Pat < 1869 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)), 1870 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset))) 1871 >; 1872 1873 // 3. No offset at all 1874 def : Pat < 1875 (constant_load i64:$sbase), 1876 (vt (Instr_IMM $sbase, 0)) 1877 >; 1878} 1879 1880defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1881defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1882defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>; 1883defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>; 1884defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, i128>; 1885defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>; 1886defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1887defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>; 1888defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>; 1889 1890//===----------------------------------------------------------------------===// 1891// MUBUF Patterns 1892//===----------------------------------------------------------------------===// 1893 1894multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 1895 PatFrag global_ld, PatFrag constant_ld> { 1896 def : Pat < 1897 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), 1898 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 1899 >; 1900 1901 def : Pat < 1902 (vt (global_ld i64:$ptr)), 1903 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1904 >; 1905 1906 def : Pat < 1907 (vt (global_ld (add i64:$ptr, i64:$offset))), 1908 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1909 >; 1910 1911 def : Pat < 1912 (vt (constant_ld (add i64:$ptr, i64:$offset))), 1913 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1914 >; 1915} 1916 1917defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, 1918 sextloadi8_global, sextloadi8_constant>; 1919defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, 1920 az_extloadi8_global, az_extloadi8_constant>; 1921defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, 1922 sextloadi16_global, sextloadi16_constant>; 1923defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, 1924 az_extloadi16_global, az_extloadi16_constant>; 1925defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, 1926 global_load, constant_load>; 1927defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1928 global_load, constant_load>; 1929defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1930 az_extloadi32_global, az_extloadi32_constant>; 1931defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, 1932 global_load, constant_load>; 1933defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, 1934 global_load, constant_load>; 1935 1936multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> { 1937 1938 def : Pat < 1939 (st vt:$value, i64:$ptr), 1940 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1941 >; 1942 1943 def : Pat < 1944 (st vt:$value, (add i64:$ptr, i64:$offset)), 1945 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0) 1946 >; 1947} 1948 1949defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>; 1950defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>; 1951defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>; 1952defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>; 1953defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>; 1954defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>; 1955 1956//===----------------------------------------------------------------------===// 1957// MTBUF Patterns 1958//===----------------------------------------------------------------------===// 1959 1960// TBUFFER_STORE_FORMAT_*, addr64=0 1961class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 1962 (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 1963 i32:$soffset, imm:$inst_offset, imm:$dfmt, 1964 imm:$nfmt, imm:$offen, imm:$idxen, 1965 imm:$glc, imm:$slc, imm:$tfe), 1966 (opcode 1967 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 1968 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 1969 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 1970>; 1971 1972def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 1973def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 1974def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 1975def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 1976 1977/********** ====================== **********/ 1978/********** Indirect adressing **********/ 1979/********** ====================== **********/ 1980 1981multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { 1982 1983 // 1. Extract with offset 1984 def : Pat< 1985 (vector_extract vt:$vec, (add i32:$idx, imm:$off)), 1986 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) 1987 >; 1988 1989 // 2. Extract without offset 1990 def : Pat< 1991 (vector_extract vt:$vec, i32:$idx), 1992 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) 1993 >; 1994 1995 // 3. Insert with offset 1996 def : Pat< 1997 (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)), 1998 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) 1999 >; 2000 2001 // 4. Insert without offset 2002 def : Pat< 2003 (vector_insert vt:$vec, f32:$val, i32:$idx), 2004 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) 2005 >; 2006} 2007 2008defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>; 2009defm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>; 2010defm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>; 2011defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>; 2012 2013/********** =============== **********/ 2014/********** Conditions **********/ 2015/********** =============== **********/ 2016 2017def : Pat< 2018 (i1 (setcc f32:$src0, f32:$src1, SETO)), 2019 (V_CMP_O_F32_e64 $src0, $src1) 2020>; 2021 2022def : Pat< 2023 (i1 (setcc f32:$src0, f32:$src1, SETUO)), 2024 (V_CMP_U_F32_e64 $src0, $src1) 2025>; 2026 2027//===----------------------------------------------------------------------===// 2028// Miscellaneous Patterns 2029//===----------------------------------------------------------------------===// 2030 2031def : Pat < 2032 (i64 (trunc i128:$x)), 2033 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2034 (i32 (EXTRACT_SUBREG $x, sub0)), sub0), 2035 (i32 (EXTRACT_SUBREG $x, sub1)), sub1) 2036>; 2037 2038def : Pat < 2039 (i32 (trunc i64:$a)), 2040 (EXTRACT_SUBREG $a, sub0) 2041>; 2042 2043def : Pat < 2044 (or i64:$a, i64:$b), 2045 (INSERT_SUBREG 2046 (INSERT_SUBREG (IMPLICIT_DEF), 2047 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub0), (EXTRACT_SUBREG $b, sub0)), sub0), 2048 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub1), (EXTRACT_SUBREG $b, sub1)), sub1) 2049>; 2050 2051//============================================================================// 2052// Miscellaneous Optimization Patterns 2053//============================================================================// 2054 2055def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>; 2056 2057} // End isSI predicate 2058