SIInstructions.td revision b52bf6a3b31596a309f4b12884522e9b4a344654
1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def isSI : Predicate<"Subtarget.getGeneration() " 26 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; 27 28def WAIT_FLAG : InstFlag<"printWaitFlag">; 29 30let Predicates = [isSI] in { 31 32let neverHasSideEffects = 1 in { 33 34let isMoveImm = 1 in { 35def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 36def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 37def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 38def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 39} // End isMoveImm = 1 40 41def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 42def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 43def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 44def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 45def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 46def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 47} // End neverHasSideEffects = 1 48 49////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 50////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 51////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 52////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 53////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 54////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 55////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 56////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 57//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 58//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 59def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 60//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 61//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 62//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 63////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 64////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 65////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 66////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 67def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 68def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 69def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 70def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 71 72let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 73 74def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 75def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 76def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 77def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 78def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 79def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 80def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 81def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 82 83} // End hasSideEffects = 1 84 85def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 86def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 87def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 88def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 89def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 90def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 91//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 92def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 93def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 94def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 95def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 96def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 97 98/* 99This instruction is disabled for now until we can figure out how to teach 100the instruction selector to correctly use the S_CMP* vs V_CMP* 101instructions. 102 103When this instruction is enabled the code generator sometimes produces this 104invalid sequence: 105 106SCC = S_CMPK_EQ_I32 SGPR0, imm 107VCC = COPY SCC 108VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 109 110def S_CMPK_EQ_I32 : SOPK < 111 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 112 "S_CMPK_EQ_I32", 113 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 114>; 115*/ 116 117let isCompare = 1 in { 118def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 119def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 120def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 121def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 122def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 123def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 124def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 125def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 126def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 127def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 128def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 129} // End isCompare = 1 130 131def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 132def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 133//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 134def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 135def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 136def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 137//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 138//def EXP : EXP_ <0x00000000, "EXP", []>; 139 140let isCompare = 1 in { 141 142defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 143defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_LT>; 144defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_EQ>; 145defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_LE>; 146defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_GT>; 147defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", f32, COND_NE>; 148defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_GE>; 149defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32">; 150defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32">; 151defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 152defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 153defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 154defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 155defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_NE>; 156defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 157defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 158 159let hasSideEffects = 1, Defs = [EXEC] in { 160 161defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 162defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 163defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 164defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 165defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 166defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 167defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 168defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 169defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 170defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 171defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 172defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 173defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 174defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 175defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 176defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 177 178} // End hasSideEffects = 1, Defs = [EXEC] 179 180defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 181defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_LT>; 182defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_EQ>; 183defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_LE>; 184defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_GT>; 185defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 186defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_GE>; 187defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64">; 188defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64">; 189defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 190defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 191defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 192defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 193defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_NE>; 194defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 195defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 196 197let hasSideEffects = 1, Defs = [EXEC] in { 198 199defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 200defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 201defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 202defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 203defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 204defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 205defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 206defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 207defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 208defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 209defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 210defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 211defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 212defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 213defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 214defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 215 216} // End hasSideEffects = 1, Defs = [EXEC] 217 218defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 219defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 220defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 221defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 222defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 223defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 224defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 225defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 226defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 227defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 228defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 229defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 230defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 231defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 232defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 233defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 234 235let hasSideEffects = 1, Defs = [EXEC] in { 236 237defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 238defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 239defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 240defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 241defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 242defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 243defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 244defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 245defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 246defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 247defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 248defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 249defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 250defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 251defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 252defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 253 254} // End hasSideEffects = 1, Defs = [EXEC] 255 256defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 257defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 258defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 259defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 260defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 261defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 262defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 263defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 264defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 265defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 266defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 267defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 268defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 269defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 270defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 271defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 272 273let hasSideEffects = 1, Defs = [EXEC] in { 274 275defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 276defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 277defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 278defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 279defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 280defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 281defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 282defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 283defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 284defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 285defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 286defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 287defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 288defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 289defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 290defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 291 292} // End hasSideEffects = 1, Defs = [EXEC] 293 294defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 295defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_LT>; 296defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 297defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_LE>; 298defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_GT>; 299defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 300defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_GE>; 301defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 302 303let hasSideEffects = 1, Defs = [EXEC] in { 304 305defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 306defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 307defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 308defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 309defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 310defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 311defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 312defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 313 314} // End hasSideEffects = 1, Defs = [EXEC] 315 316defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 317defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64">; 318defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64">; 319defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64">; 320defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64">; 321defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64">; 322defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64">; 323defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 324 325let hasSideEffects = 1, Defs = [EXEC] in { 326 327defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 328defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 329defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 330defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 331defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 332defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 333defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 334defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 335 336} // End hasSideEffects = 1, Defs = [EXEC] 337 338defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 339defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32">; 340defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32">; 341defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32">; 342defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32">; 343defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32">; 344defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32">; 345defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 346 347let hasSideEffects = 1, Defs = [EXEC] in { 348 349defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 350defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 351defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 352defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 353defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 354defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 355defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 356defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 357 358} // End hasSideEffects = 1, Defs = [EXEC] 359 360defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 361defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64">; 362defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64">; 363defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64">; 364defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64">; 365defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64">; 366defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64">; 367defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 368 369let hasSideEffects = 1, Defs = [EXEC] in { 370 371defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 372defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 373defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 374defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 375defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 376defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 377defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 378defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 379 380} // End hasSideEffects = 1, Defs = [EXEC] 381 382defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 383 384let hasSideEffects = 1, Defs = [EXEC] in { 385defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 386} // End hasSideEffects = 1, Defs = [EXEC] 387 388defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 389 390let hasSideEffects = 1, Defs = [EXEC] in { 391defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 392} // End hasSideEffects = 1, Defs = [EXEC] 393 394} // End isCompare = 1 395 396def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>; 397def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>; 398def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; 399def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>; 400def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>; 401def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>; 402def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>; 403def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>; 404def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>; 405def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; 406 407//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 408//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 409//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 410defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 411//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 412//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 413//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 414//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 415defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; 416defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>; 417defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>; 418defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>; 419defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 420defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 421defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 422 423def BUFFER_STORE_BYTE : MUBUF_Store_Helper < 424 0x00000018, "BUFFER_STORE_BYTE", VReg_32 425>; 426 427def BUFFER_STORE_SHORT : MUBUF_Store_Helper < 428 0x0000001a, "BUFFER_STORE_SHORT", VReg_32 429>; 430 431def BUFFER_STORE_DWORD : MUBUF_Store_Helper < 432 0x0000001c, "BUFFER_STORE_DWORD", VReg_32 433>; 434 435def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 436 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64 437>; 438 439def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 440 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128 441>; 442//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 443//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 444//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 445//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 446//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 447//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 448//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 449//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 450//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 451//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 452//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 453//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 454//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 455//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 456//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 457//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 458//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 459//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 460//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 461//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 462//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 463//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 464//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 465//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 466//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 467//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 468//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 469//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 470//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 471//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 472//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 473//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 474//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 475//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 476//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 477//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 478//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 479//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 480//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 481def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 482def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; 483def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; 484def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; 485def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; 486 487let mayLoad = 1 in { 488 489defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SReg_32>; 490defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 491defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 492defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 493defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 494 495defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 496 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SReg_32 497>; 498 499defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 500 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 501>; 502 503defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 504 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 505>; 506 507defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 508 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 509>; 510 511defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 512 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 513>; 514 515} // mayLoad = 1 516 517//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 518//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 519defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">; 520defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">; 521//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 522//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 523//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 524//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 525//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 526//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 527//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 528//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 529defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">; 530//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 531//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 532//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 533//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 534//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 535//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 536//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 537//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 538//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 539//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 540//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 541//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 542//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 543//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 544//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 545//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 546//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 547defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; 548//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 549defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; 550//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 551defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; 552defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; 553//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 554//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 555defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; 556//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 557defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; 558//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 559defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; 560defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; 561//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 562//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 563//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 564//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 565//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 566//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 567//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 568//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 569//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 570//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 571//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 572//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 573//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 574//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 575//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 576//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 577//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 578//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 579//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 580//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 581//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 582//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 583//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 584//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 585//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 586//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 587//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 588//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 589//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 590//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 591//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 592//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 593//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 594//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 595//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 596//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 597//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 598//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 599//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 600//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 601//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 602//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 603//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 604//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 605//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 606//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 607//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 608//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 609//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 610//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 611//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 612//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 613//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 614//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 615 616 617let neverHasSideEffects = 1, isMoveImm = 1 in { 618defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 619} // End neverHasSideEffects = 1, isMoveImm = 1 620 621defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 622defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", 623 [(set i32:$dst, (fp_to_sint f64:$src0))] 624>; 625defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32", 626 [(set f64:$dst, (sint_to_fp i32:$src0))] 627>; 628defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 629 [(set f32:$dst, (sint_to_fp i32:$src0))] 630>; 631defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", 632 [(set f32:$dst, (uint_to_fp i32:$src0))] 633>; 634defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", 635 [(set i32:$dst, (fp_to_uint f32:$src0))] 636>; 637defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 638 [(set i32:$dst, (fp_to_sint f32:$src0))] 639>; 640defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 641////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 642//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 643//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 644//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 645//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 646defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64", 647 [(set f32:$dst, (fround f64:$src0))] 648>; 649defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32", 650 [(set f64:$dst, (fextend f32:$src0))] 651>; 652//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 653//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 654//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 655//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 656//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 657//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 658defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 659 [(set f32:$dst, (AMDGPUfract f32:$src0))] 660>; 661defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", 662 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] 663>; 664defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 665 [(set f32:$dst, (fceil f32:$src0))] 666>; 667defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 668 [(set f32:$dst, (frint f32:$src0))] 669>; 670defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 671 [(set f32:$dst, (ffloor f32:$src0))] 672>; 673defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 674 [(set f32:$dst, (fexp2 f32:$src0))] 675>; 676defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 677defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 678 [(set f32:$dst, (flog2 f32:$src0))] 679>; 680defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 681defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 682defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 683 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 684>; 685defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 686defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 687defm V_RSQ_LEGACY_F32 : VOP1_32 < 688 0x0000002d, "V_RSQ_LEGACY_F32", 689 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] 690>; 691defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 692defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", 693 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))] 694>; 695defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 696defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 697defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 698defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", 699 [(set f32:$dst, (fsqrt f32:$src0))] 700>; 701defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", 702 [(set f64:$dst, (fsqrt f64:$src0))] 703>; 704defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 705defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 706defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 707defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 708defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 709defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 710defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 711//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 712defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 713defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 714//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 715defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 716//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 717defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 718defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 719defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 720 721def V_INTERP_P1_F32 : VINTRP < 722 0x00000000, 723 (outs VReg_32:$dst), 724 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 725 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 726 []> { 727 let DisableEncoding = "$m0"; 728} 729 730def V_INTERP_P2_F32 : VINTRP < 731 0x00000001, 732 (outs VReg_32:$dst), 733 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 734 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 735 []> { 736 737 let Constraints = "$src0 = $dst"; 738 let DisableEncoding = "$src0,$m0"; 739 740} 741 742def V_INTERP_MOV_F32 : VINTRP < 743 0x00000002, 744 (outs VReg_32:$dst), 745 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 746 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 747 []> { 748 let DisableEncoding = "$m0"; 749} 750 751//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 752 753let isTerminator = 1 in { 754 755def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 756 [(IL_retflag)]> { 757 let SIMM16 = 0; 758 let isBarrier = 1; 759 let hasCtrlDep = 1; 760} 761 762let isBranch = 1 in { 763def S_BRANCH : SOPP < 764 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 765 [(br bb:$target)]> { 766 let isBarrier = 1; 767} 768 769let DisableEncoding = "$scc" in { 770def S_CBRANCH_SCC0 : SOPP < 771 0x00000004, (ins brtarget:$target, SCCReg:$scc), 772 "S_CBRANCH_SCC0 $target", [] 773>; 774def S_CBRANCH_SCC1 : SOPP < 775 0x00000005, (ins brtarget:$target, SCCReg:$scc), 776 "S_CBRANCH_SCC1 $target", 777 [] 778>; 779} // End DisableEncoding = "$scc" 780 781def S_CBRANCH_VCCZ : SOPP < 782 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 783 "S_CBRANCH_VCCZ $target", 784 [] 785>; 786def S_CBRANCH_VCCNZ : SOPP < 787 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 788 "S_CBRANCH_VCCNZ $target", 789 [] 790>; 791 792let DisableEncoding = "$exec" in { 793def S_CBRANCH_EXECZ : SOPP < 794 0x00000008, (ins brtarget:$target, EXECReg:$exec), 795 "S_CBRANCH_EXECZ $target", 796 [] 797>; 798def S_CBRANCH_EXECNZ : SOPP < 799 0x00000009, (ins brtarget:$target, EXECReg:$exec), 800 "S_CBRANCH_EXECNZ $target", 801 [] 802>; 803} // End DisableEncoding = "$exec" 804 805 806} // End isBranch = 1 807} // End isTerminator = 1 808 809let hasSideEffects = 1 in { 810def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", 811 [(int_AMDGPU_barrier_local)] 812> { 813 let SIMM16 = 0; 814 let isBarrier = 1; 815 let hasCtrlDep = 1; 816 let mayLoad = 1; 817 let mayStore = 1; 818} 819 820def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16", 821 [] 822>; 823} // End hasSideEffects 824//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 825//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 826//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 827//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>; 828//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 829//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 830//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 831//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 832//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 833//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 834 835def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 836 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 837 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 838 [] 839>{ 840 let DisableEncoding = "$vcc"; 841} 842 843def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 844 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 845 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 846 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 847 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] 848>; 849 850//f32 pattern for V_CNDMASK_B32_e64 851def : Pat < 852 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 853 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 854>; 855 856def : Pat < 857 (i32 (trunc i64:$val)), 858 (EXTRACT_SUBREG $val, sub0) 859>; 860 861//use two V_CNDMASK_B32_e64 instructions for f64 862def : Pat < 863 (f64 (select i1:$src2, f64:$src1, f64:$src0)), 864 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 865 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0), 866 (EXTRACT_SUBREG $src1, sub0), 867 $src2), sub0), 868 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1), 869 (EXTRACT_SUBREG $src1, sub1), 870 $src2), sub1) 871>; 872 873defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 874defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 875 876let isCommutable = 1 in { 877defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 878 [(set f32:$dst, (fadd f32:$src0, f32:$src1))] 879>; 880 881defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 882 [(set f32:$dst, (fsub f32:$src0, f32:$src1))] 883>; 884defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 885} // End isCommutable = 1 886 887defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 888 889let isCommutable = 1 in { 890 891defm V_MUL_LEGACY_F32 : VOP2_32 < 892 0x00000007, "V_MUL_LEGACY_F32", 893 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] 894>; 895 896defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 897 [(set f32:$dst, (fmul f32:$src0, f32:$src1))] 898>; 899 900 901defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", 902 [(set i32:$dst, (mul I24:$src0, I24:$src1))] 903>; 904//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 905defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", 906 [(set i32:$dst, (mul U24:$src0, U24:$src1))] 907>; 908//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 909 910 911defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 912 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] 913>; 914 915defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 916 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] 917>; 918 919defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 920defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 921defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", 922 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] 923>; 924defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", 925 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] 926>; 927defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", 928 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] 929>; 930defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", 931 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] 932>; 933 934defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", 935 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 936>; 937defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 938 939defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", 940 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 941>; 942defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 943 944let hasPostISelHook = 1 in { 945 946defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 947 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 948>; 949 950} 951defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 952 953defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 954 [(set i32:$dst, (and i32:$src0, i32:$src1))] 955>; 956defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 957 [(set i32:$dst, (or i32:$src0, i32:$src1))] 958>; 959defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 960 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 961>; 962 963} // End isCommutable = 1 964 965defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 966defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 967defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 968defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 969//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 970defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 971defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 972 973let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 974defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", 975 [(set i32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))] 976>; 977 978defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", 979 [(set i32:$dst, (sub i32:$src0, i32:$src1))] 980>; 981defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">; 982 983let Uses = [VCC] in { // Carry-out comes from VCC 984defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>; 985defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>; 986defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">; 987} // End Uses = [VCC] 988} // End isCommutable = 1, Defs = [VCC] 989 990defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 991////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 992////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 993////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 994defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 995 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] 996>; 997////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 998////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 999def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 1000def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 1001def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 1002def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 1003def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 1004def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 1005def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 1006def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 1007def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 1008def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 1009def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 1010def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 1011////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 1012////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 1013////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 1014////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 1015//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 1016 1017let neverHasSideEffects = 1 in { 1018 1019def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 1020def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 1021def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", 1022 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))] 1023>; 1024def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", 1025 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))] 1026>; 1027 1028} // End neverHasSideEffects 1029def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 1030def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 1031def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 1032def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 1033def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 1034def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 1035def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 1036defm : BFIPatterns <V_BFI_B32>; 1037def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", 1038 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))] 1039>; 1040def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", 1041 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 1042>; 1043//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 1044def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 1045def : ROTRPattern <V_ALIGNBIT_B32>; 1046 1047def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 1048def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 1049////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 1050////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 1051////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 1052////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 1053////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 1054////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 1055////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 1056////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 1057////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 1058//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 1059//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 1060//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 1061def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 1062////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 1063def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 1064def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 1065 1066def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64", 1067 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1068>; 1069def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64", 1070 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1071>; 1072def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64", 1073 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1074>; 1075 1076let isCommutable = 1 in { 1077 1078def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 1079def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 1080def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 1081def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 1082 1083} // isCommutable = 1 1084 1085def : Pat < 1086 (fadd f64:$src0, f64:$src1), 1087 (V_ADD_F64 $src0, $src1, (i64 0)) 1088>; 1089 1090def : Pat < 1091 (fmul f64:$src0, f64:$src1), 1092 (V_MUL_F64 $src0, $src1, (i64 0)) 1093>; 1094 1095def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 1096 1097let isCommutable = 1 in { 1098 1099def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 1100def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 1101def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 1102def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 1103 1104} // isCommutable = 1 1105 1106def : Pat < 1107 (mul i32:$src0, i32:$src1), 1108 (V_MUL_LO_I32 $src0, $src1, (i32 0)) 1109>; 1110 1111def : Pat < 1112 (mulhu i32:$src0, i32:$src1), 1113 (V_MUL_HI_U32 $src0, $src1, (i32 0)) 1114>; 1115 1116def : Pat < 1117 (mulhs i32:$src0, i32:$src1), 1118 (V_MUL_HI_I32 $src0, $src1, (i32 0)) 1119>; 1120 1121def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1122def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1123def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1124def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1125//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1126//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1127//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1128def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1129def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 1130def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 1131def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", []>; 1132def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", []>; 1133def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>; 1134def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>; 1135def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 1136def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 1137def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 1138def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 1139 1140def S_CSELECT_B32 : SOP2 < 1141 0x0000000a, (outs SReg_32:$dst), 1142 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1143 [] 1144>; 1145 1146def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1147 1148def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 1149 1150def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1151 [(set i64:$dst, (and i64:$src0, i64:$src1))] 1152>; 1153 1154def : Pat < 1155 (i1 (and i1:$src0, i1:$src1)), 1156 (S_AND_B64 $src0, $src1) 1157>; 1158 1159def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 1160def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 1161def : Pat < 1162 (i1 (or i1:$src0, i1:$src1)), 1163 (S_OR_B64 $src0, $src1) 1164>; 1165def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 1166def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", 1167 [(set i1:$dst, (xor i1:$src0, i1:$src1))] 1168>; 1169def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1170def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1171def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1172def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1173def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1174def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1175def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1176def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1177def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1178def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1179 1180// Use added complexity so these patterns are preferred to the VALU patterns. 1181let AddedComplexity = 1 in { 1182 1183def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", 1184 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 1185>; 1186def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64", 1187 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1188>; 1189def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", 1190 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 1191>; 1192def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64", 1193 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1194>; 1195def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", 1196 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 1197>; 1198def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64", 1199 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1200>; 1201 1202} // End AddedComplexity = 1 1203 1204def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1205def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1206def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1207def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1208def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1209def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1210def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1211//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1212def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1213 1214let isCodeGenOnly = 1, isPseudo = 1 in { 1215 1216def LOAD_CONST : AMDGPUShaderInst < 1217 (outs GPRF32:$dst), 1218 (ins i32imm:$src), 1219 "LOAD_CONST $dst, $src", 1220 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1221>; 1222 1223// SI pseudo instructions. These are used by the CFG structurizer pass 1224// and should be lowered to ISA instructions prior to codegen. 1225 1226let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1227 Uses = [EXEC], Defs = [EXEC] in { 1228 1229let isBranch = 1, isTerminator = 1 in { 1230 1231def SI_IF : InstSI < 1232 (outs SReg_64:$dst), 1233 (ins SReg_64:$vcc, brtarget:$target), 1234 "SI_IF $dst, $vcc, $target", 1235 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1236>; 1237 1238def SI_ELSE : InstSI < 1239 (outs SReg_64:$dst), 1240 (ins SReg_64:$src, brtarget:$target), 1241 "SI_ELSE $dst, $src, $target", 1242 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> { 1243 1244 let Constraints = "$src = $dst"; 1245} 1246 1247def SI_LOOP : InstSI < 1248 (outs), 1249 (ins SReg_64:$saved, brtarget:$target), 1250 "SI_LOOP $saved, $target", 1251 [(int_SI_loop i64:$saved, bb:$target)] 1252>; 1253 1254} // end isBranch = 1, isTerminator = 1 1255 1256def SI_BREAK : InstSI < 1257 (outs SReg_64:$dst), 1258 (ins SReg_64:$src), 1259 "SI_ELSE $dst, $src", 1260 [(set i64:$dst, (int_SI_break i64:$src))] 1261>; 1262 1263def SI_IF_BREAK : InstSI < 1264 (outs SReg_64:$dst), 1265 (ins SReg_64:$vcc, SReg_64:$src), 1266 "SI_IF_BREAK $dst, $vcc, $src", 1267 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1268>; 1269 1270def SI_ELSE_BREAK : InstSI < 1271 (outs SReg_64:$dst), 1272 (ins SReg_64:$src0, SReg_64:$src1), 1273 "SI_ELSE_BREAK $dst, $src0, $src1", 1274 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1275>; 1276 1277def SI_END_CF : InstSI < 1278 (outs), 1279 (ins SReg_64:$saved), 1280 "SI_END_CF $saved", 1281 [(int_SI_end_cf i64:$saved)] 1282>; 1283 1284def SI_KILL : InstSI < 1285 (outs), 1286 (ins VReg_32:$src), 1287 "SI_KIL $src", 1288 [(int_AMDGPU_kill f32:$src)] 1289>; 1290 1291} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1292 // Uses = [EXEC], Defs = [EXEC] 1293 1294let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1295 1296def SI_INDIRECT_SRC : InstSI < 1297 (outs VReg_32:$dst, SReg_64:$temp), 1298 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1299 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1300 [] 1301>; 1302 1303class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1304 (outs rc:$dst, SReg_64:$temp), 1305 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1306 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1307 [] 1308> { 1309 let Constraints = "$src = $dst"; 1310} 1311 1312def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1313def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1314def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1315def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1316 1317} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1318 1319let usesCustomInserter = 1 in { 1320 1321// This pseudo instruction takes a pointer as input and outputs a resource 1322// constant that can be used with the ADDR64 MUBUF instructions. 1323def SI_ADDR64_RSRC : InstSI < 1324 (outs SReg_128:$srsrc), 1325 (ins SReg_64:$ptr), 1326 "", [] 1327>; 1328 1329def V_SUB_F64 : InstSI < 1330 (outs VReg_64:$dst), 1331 (ins VReg_64:$src0, VReg_64:$src1), 1332 "V_SUB_F64 $dst, $src0, $src1", 1333 [] 1334>; 1335 1336} // end usesCustomInserter 1337 1338} // end IsCodeGenOnly, isPseudo 1339 1340def : Pat< 1341 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 1342 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) 1343>; 1344 1345def : Pat < 1346 (int_AMDGPU_kilp), 1347 (SI_KILL (V_MOV_B32_e32 0xbf800000)) 1348>; 1349 1350/* int_SI_vs_load_input */ 1351def : Pat< 1352 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr), 1353 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset) 1354>; 1355 1356/* int_SI_export */ 1357def : Pat < 1358 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1359 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 1360 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1361 $src0, $src1, $src2, $src3) 1362>; 1363 1364def : Pat < 1365 (f64 (fsub f64:$src0, f64:$src1)), 1366 (V_SUB_F64 $src0, $src1) 1367>; 1368 1369/********** ======================= **********/ 1370/********** Image sampling patterns **********/ 1371/********** ======================= **********/ 1372 1373/* SIsample for simple 1D texture lookup */ 1374def : Pat < 1375 (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm), 1376 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1377>; 1378 1379class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1380 (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm), 1381 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1382>; 1383 1384class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1385 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT), 1386 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1387>; 1388 1389class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1390 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY), 1391 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1392>; 1393 1394class SampleShadowPattern<SDNode name, MIMG opcode, 1395 ValueType vt> : Pat < 1396 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW), 1397 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1398>; 1399 1400class SampleShadowArrayPattern<SDNode name, MIMG opcode, 1401 ValueType vt> : Pat < 1402 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY), 1403 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1404>; 1405 1406/* SIsample* for texture lookups consuming more address parameters */ 1407multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 1408 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 1409MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 1410 def : SamplePattern <SIsample, sample, addr_type>; 1411 def : SampleRectPattern <SIsample, sample, addr_type>; 1412 def : SampleArrayPattern <SIsample, sample, addr_type>; 1413 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 1414 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 1415 1416 def : SamplePattern <SIsamplel, sample_l, addr_type>; 1417 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 1418 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 1419 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 1420 1421 def : SamplePattern <SIsampleb, sample_b, addr_type>; 1422 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 1423 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 1424 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 1425 1426 def : SamplePattern <SIsampled, sample_d, addr_type>; 1427 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 1428 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 1429 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 1430} 1431 1432defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 1433 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 1434 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 1435 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 1436 v2i32>; 1437defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 1438 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 1439 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 1440 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 1441 v4i32>; 1442defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 1443 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 1444 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 1445 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 1446 v8i32>; 1447defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 1448 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 1449 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 1450 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 1451 v16i32>; 1452 1453/* int_SI_imageload for texture fetches consuming varying address parameters */ 1454class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1455 (name addr_type:$addr, v32i8:$rsrc, imm), 1456 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1457>; 1458 1459class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1460 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 1461 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1462>; 1463 1464class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1465 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA), 1466 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1467>; 1468 1469class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1470 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA), 1471 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1472>; 1473 1474multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> { 1475 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>; 1476 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>; 1477} 1478 1479multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> { 1480 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>; 1481 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>; 1482} 1483 1484defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>; 1485defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>; 1486 1487defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>; 1488defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>; 1489 1490/* Image resource information */ 1491def : Pat < 1492 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 1493 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1494>; 1495 1496def : Pat < 1497 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 1498 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1499>; 1500 1501def : Pat < 1502 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA), 1503 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1504>; 1505 1506/********** ============================================ **********/ 1507/********** Extraction, Insertion, Building and Casting **********/ 1508/********** ============================================ **********/ 1509 1510foreach Index = 0-2 in { 1511 def Extract_Element_v2i32_#Index : Extract_Element < 1512 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1513 >; 1514 def Insert_Element_v2i32_#Index : Insert_Element < 1515 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1516 >; 1517 1518 def Extract_Element_v2f32_#Index : Extract_Element < 1519 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1520 >; 1521 def Insert_Element_v2f32_#Index : Insert_Element < 1522 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1523 >; 1524} 1525 1526foreach Index = 0-3 in { 1527 def Extract_Element_v4i32_#Index : Extract_Element < 1528 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1529 >; 1530 def Insert_Element_v4i32_#Index : Insert_Element < 1531 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1532 >; 1533 1534 def Extract_Element_v4f32_#Index : Extract_Element < 1535 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1536 >; 1537 def Insert_Element_v4f32_#Index : Insert_Element < 1538 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1539 >; 1540} 1541 1542foreach Index = 0-7 in { 1543 def Extract_Element_v8i32_#Index : Extract_Element < 1544 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1545 >; 1546 def Insert_Element_v8i32_#Index : Insert_Element < 1547 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1548 >; 1549 1550 def Extract_Element_v8f32_#Index : Extract_Element < 1551 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1552 >; 1553 def Insert_Element_v8f32_#Index : Insert_Element < 1554 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1555 >; 1556} 1557 1558foreach Index = 0-15 in { 1559 def Extract_Element_v16i32_#Index : Extract_Element < 1560 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1561 >; 1562 def Insert_Element_v16i32_#Index : Insert_Element < 1563 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1564 >; 1565 1566 def Extract_Element_v16f32_#Index : Extract_Element < 1567 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1568 >; 1569 def Insert_Element_v16f32_#Index : Insert_Element < 1570 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1571 >; 1572} 1573 1574def : BitConvert <i32, f32, SReg_32>; 1575def : BitConvert <i32, f32, VReg_32>; 1576 1577def : BitConvert <f32, i32, SReg_32>; 1578def : BitConvert <f32, i32, VReg_32>; 1579 1580def : BitConvert <i64, f64, VReg_64>; 1581 1582def : BitConvert <f64, i64, VReg_64>; 1583 1584def : BitConvert <v2f32, v2i32, VReg_64>; 1585def : BitConvert <v2i32, v2f32, VReg_64>; 1586def : BitConvert <v2i32, i64, VReg_64>; 1587 1588def : BitConvert <v4f32, v4i32, VReg_128>; 1589def : BitConvert <v4i32, v4f32, VReg_128>; 1590def : BitConvert <v4i32, i128, VReg_128>; 1591def : BitConvert <i128, v4i32, VReg_128>; 1592 1593def : BitConvert <v8i32, v32i8, SReg_256>; 1594def : BitConvert <v32i8, v8i32, SReg_256>; 1595def : BitConvert <v8i32, v32i8, VReg_256>; 1596def : BitConvert <v32i8, v8i32, VReg_256>; 1597 1598/********** =================== **********/ 1599/********** Src & Dst modifiers **********/ 1600/********** =================== **********/ 1601 1602def : Pat < 1603 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1604 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1605 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1606>; 1607 1608def : Pat < 1609 (fabs f32:$src), 1610 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1611 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1612>; 1613 1614def : Pat < 1615 (fneg f32:$src), 1616 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1617 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */) 1618>; 1619 1620/********** ================== **********/ 1621/********** Immediate Patterns **********/ 1622/********** ================== **********/ 1623 1624def : Pat < 1625 (SGPRImm<(i32 imm)>:$imm), 1626 (S_MOV_B32 imm:$imm) 1627>; 1628 1629def : Pat < 1630 (SGPRImm<(f32 fpimm)>:$imm), 1631 (S_MOV_B32 fpimm:$imm) 1632>; 1633 1634def : Pat < 1635 (i32 imm:$imm), 1636 (V_MOV_B32_e32 imm:$imm) 1637>; 1638 1639def : Pat < 1640 (f32 fpimm:$imm), 1641 (V_MOV_B32_e32 fpimm:$imm) 1642>; 1643 1644def : Pat < 1645 (i1 imm:$imm), 1646 (S_MOV_B64 imm:$imm) 1647>; 1648 1649def : Pat < 1650 (i64 InlineImm<i64>:$imm), 1651 (S_MOV_B64 InlineImm<i64>:$imm) 1652>; 1653 1654// i64 immediates aren't supported in hardware, split it into two 32bit values 1655def : Pat < 1656 (i64 imm:$imm), 1657 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1658 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1659 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1660>; 1661 1662def : Pat < 1663 (f64 fpimm:$imm), 1664 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 1665 (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0), 1666 (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1) 1667>; 1668 1669/********** ===================== **********/ 1670/********** Interpolation Paterns **********/ 1671/********** ===================== **********/ 1672 1673def : Pat < 1674 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params), 1675 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params) 1676>; 1677 1678def : Pat < 1679 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij), 1680 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0), 1681 imm:$attr_chan, imm:$attr, i32:$params), 1682 (EXTRACT_SUBREG $ij, sub1), 1683 imm:$attr_chan, imm:$attr, $params) 1684>; 1685 1686/********** ================== **********/ 1687/********** Intrinsic Patterns **********/ 1688/********** ================== **********/ 1689 1690/* llvm.AMDGPU.pow */ 1691def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 1692 1693def : Pat < 1694 (int_AMDGPU_div f32:$src0, f32:$src1), 1695 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 1696>; 1697 1698def : Pat< 1699 (fdiv f32:$src0, f32:$src1), 1700 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) 1701>; 1702 1703def : Pat< 1704 (fdiv f64:$src0, f64:$src1), 1705 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) 1706>; 1707 1708def : Pat < 1709 (fcos f32:$src0), 1710 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1711>; 1712 1713def : Pat < 1714 (fsin f32:$src0), 1715 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1716>; 1717 1718def : Pat < 1719 (int_AMDGPU_cube v4f32:$src), 1720 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1721 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), 1722 (EXTRACT_SUBREG $src, sub1), 1723 (EXTRACT_SUBREG $src, sub2)), 1724 sub0), 1725 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), 1726 (EXTRACT_SUBREG $src, sub1), 1727 (EXTRACT_SUBREG $src, sub2)), 1728 sub1), 1729 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), 1730 (EXTRACT_SUBREG $src, sub1), 1731 (EXTRACT_SUBREG $src, sub2)), 1732 sub2), 1733 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), 1734 (EXTRACT_SUBREG $src, sub1), 1735 (EXTRACT_SUBREG $src, sub2)), 1736 sub3) 1737>; 1738 1739def : Pat < 1740 (i32 (sext i1:$src0)), 1741 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 1742>; 1743 1744// 1. Offset as 8bit DWORD immediate 1745def : Pat < 1746 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset), 1747 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset) 1748>; 1749 1750// 2. Offset loaded in an 32bit SGPR 1751def : Pat < 1752 (SIload_constant i128:$sbase, imm:$offset), 1753 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) 1754>; 1755 1756// 3. Offset in an 32Bit VGPR 1757def : Pat < 1758 (SIload_constant i128:$sbase, i32:$voff), 1759 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff) 1760>; 1761 1762// The multiplication scales from [0,1] to the unsigned integer range 1763def : Pat < 1764 (AMDGPUurecip i32:$src0), 1765 (V_CVT_U32_F32_e32 1766 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 1767 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 1768>; 1769 1770def : Pat < 1771 (int_SI_tid), 1772 (V_MBCNT_HI_U32_B32_e32 0xffffffff, 1773 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0)) 1774>; 1775 1776/********** ================== **********/ 1777/********** VOP3 Patterns **********/ 1778/********** ================== **********/ 1779 1780def : Pat < 1781 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)), 1782 (V_MAD_F32 $src0, $src1, $src2) 1783>; 1784 1785/********** ======================= **********/ 1786/********** Load/Store Patterns **********/ 1787/********** ======================= **********/ 1788 1789class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat < 1790 (frag i32:$src0), 1791 (vt (inst 0, $src0, $src0, $src0, 0, 0)) 1792>; 1793 1794def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>; 1795def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>; 1796def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>; 1797def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>; 1798def : DSReadPat <DS_READ_B32, i32, local_load>; 1799def : Pat < 1800 (local_load i32:$src0), 1801 (i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0)) 1802>; 1803 1804class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat < 1805 (frag i32:$src1, i32:$src0), 1806 (inst 0, $src0, $src1, $src1, 0, 0) 1807>; 1808 1809def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>; 1810def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>; 1811def : DSWritePat <DS_WRITE_B32, i32, local_store>; 1812 1813def : Pat <(atomic_load_add_local i32:$ptr, i32:$val), 1814 (DS_ADD_U32_RTN 0, $ptr, $val, 0, 0)>; 1815 1816def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val), 1817 (DS_SUB_U32_RTN 0, $ptr, $val, 0, 0)>; 1818 1819/********** ================== **********/ 1820/********** SMRD Patterns **********/ 1821/********** ================== **********/ 1822 1823multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1824 1825 // 1. Offset as 8bit DWORD immediate 1826 def : Pat < 1827 (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)), 1828 (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset)) 1829 >; 1830 1831 // 2. Offset loaded in an 32bit SGPR 1832 def : Pat < 1833 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)), 1834 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset))) 1835 >; 1836 1837 // 3. No offset at all 1838 def : Pat < 1839 (constant_load i64:$sbase), 1840 (vt (Instr_IMM $sbase, 0)) 1841 >; 1842} 1843 1844defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1845defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1846defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>; 1847defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>; 1848defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, i128>; 1849defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>; 1850defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1851defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>; 1852defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>; 1853 1854//===----------------------------------------------------------------------===// 1855// MUBUF Patterns 1856//===----------------------------------------------------------------------===// 1857 1858multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 1859 PatFrag global_ld, PatFrag constant_ld> { 1860 def : Pat < 1861 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), 1862 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 1863 >; 1864 1865 def : Pat < 1866 (vt (global_ld i64:$ptr)), 1867 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1868 >; 1869 1870 def : Pat < 1871 (vt (global_ld (add i64:$ptr, i64:$offset))), 1872 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1873 >; 1874 1875 def : Pat < 1876 (vt (constant_ld (add i64:$ptr, i64:$offset))), 1877 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1878 >; 1879} 1880 1881defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, 1882 sextloadi8_global, sextloadi8_constant>; 1883defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, 1884 az_extloadi8_global, az_extloadi8_constant>; 1885defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, 1886 sextloadi16_global, sextloadi16_constant>; 1887defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, 1888 az_extloadi16_global, az_extloadi16_constant>; 1889defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, 1890 global_load, constant_load>; 1891defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1892 global_load, constant_load>; 1893defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1894 az_extloadi32_global, az_extloadi32_constant>; 1895defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, 1896 global_load, constant_load>; 1897defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, 1898 global_load, constant_load>; 1899 1900multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> { 1901 1902 def : Pat < 1903 (st vt:$value, i64:$ptr), 1904 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1905 >; 1906 1907 def : Pat < 1908 (st vt:$value, (add i64:$ptr, i64:$offset)), 1909 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0) 1910 >; 1911} 1912 1913defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>; 1914defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>; 1915defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>; 1916defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>; 1917defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>; 1918defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>; 1919 1920//===----------------------------------------------------------------------===// 1921// MTBUF Patterns 1922//===----------------------------------------------------------------------===// 1923 1924// TBUFFER_STORE_FORMAT_*, addr64=0 1925class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 1926 (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 1927 i32:$soffset, imm:$inst_offset, imm:$dfmt, 1928 imm:$nfmt, imm:$offen, imm:$idxen, 1929 imm:$glc, imm:$slc, imm:$tfe), 1930 (opcode 1931 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 1932 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 1933 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 1934>; 1935 1936def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 1937def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 1938def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 1939def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 1940 1941/********** ====================== **********/ 1942/********** Indirect adressing **********/ 1943/********** ====================== **********/ 1944 1945multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { 1946 1947 // 1. Extract with offset 1948 def : Pat< 1949 (vector_extract vt:$vec, (add i32:$idx, imm:$off)), 1950 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) 1951 >; 1952 1953 // 2. Extract without offset 1954 def : Pat< 1955 (vector_extract vt:$vec, i32:$idx), 1956 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) 1957 >; 1958 1959 // 3. Insert with offset 1960 def : Pat< 1961 (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)), 1962 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) 1963 >; 1964 1965 // 4. Insert without offset 1966 def : Pat< 1967 (vector_insert vt:$vec, f32:$val, i32:$idx), 1968 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) 1969 >; 1970} 1971 1972defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>; 1973defm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>; 1974defm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>; 1975defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>; 1976 1977/********** =============== **********/ 1978/********** Conditions **********/ 1979/********** =============== **********/ 1980 1981def : Pat< 1982 (i1 (setcc f32:$src0, f32:$src1, SETO)), 1983 (V_CMP_O_F32_e64 $src0, $src1) 1984>; 1985 1986def : Pat< 1987 (i1 (setcc f32:$src0, f32:$src1, SETUO)), 1988 (V_CMP_U_F32_e64 $src0, $src1) 1989>; 1990 1991//============================================================================// 1992// Miscellaneous Patterns 1993//===----------------------------------------------------------------------===// 1994 1995def : Pat < 1996 (i64 (trunc i128:$x)), 1997 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1998 (i32 (EXTRACT_SUBREG $x, sub0)), sub0), 1999 (i32 (EXTRACT_SUBREG $x, sub1)), sub1) 2000>; 2001 2002def : Pat < 2003 (or i64:$a, i64:$b), 2004 (INSERT_SUBREG 2005 (INSERT_SUBREG (IMPLICIT_DEF), 2006 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub0), (EXTRACT_SUBREG $b, sub0)), sub0), 2007 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub1), (EXTRACT_SUBREG $b, sub1)), sub1) 2008>; 2009 2010//============================================================================// 2011// Miscellaneous Optimization Patterns 2012//============================================================================// 2013 2014def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>; 2015 2016} // End isSI predicate 2017