SIInstructions.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def SendMsgImm : Operand<i32> { 26 let PrintMethod = "printSendMsg"; 27} 28 29def isSI : Predicate<"Subtarget.getGeneration() " 30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; 31 32def isCI : Predicate<"Subtarget.getGeneration() " 33 ">= AMDGPUSubtarget::SEA_ISLANDS">; 34 35def isCFDepth0 : Predicate<"isCFDepth0()">; 36 37def WAIT_FLAG : InstFlag<"printWaitFlag">; 38 39let SubtargetPredicate = isSI in { 40let OtherPredicates = [isCFDepth0] in { 41 42//===----------------------------------------------------------------------===// 43// SMRD Instructions 44//===----------------------------------------------------------------------===// 45 46let mayLoad = 1 in { 47 48// We are using the SGPR_32 and not the SReg_32 register class for 32-bit 49// SMRD instructions, because the SGPR_32 register class does not include M0 50// and writing to M0 from an SMRD instruction will hang the GPU. 51defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>; 52defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 53defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 54defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 55defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 56 57defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 58 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32 59>; 60 61defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 62 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 63>; 64 65defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 66 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 67>; 68 69defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 70 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 71>; 72 73defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 74 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 75>; 76 77} // mayLoad = 1 78 79//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 80//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 81 82//===----------------------------------------------------------------------===// 83// SOP1 Instructions 84//===----------------------------------------------------------------------===// 85 86let neverHasSideEffects = 1 in { 87 88let isMoveImm = 1 in { 89def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 90def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 91def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 92def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 93} // End isMoveImm = 1 94 95def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", 96 [(set i32:$dst, (not i32:$src0))] 97>; 98 99def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 100def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 101def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 102def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 103def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 104} // End neverHasSideEffects = 1 105 106////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 107////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 108////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 109////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 110////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 111////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 112////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 113////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 114//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 115//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 116def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 117//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 118def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", 119 [(set i32:$dst, (sext_inreg i32:$src0, i8))] 120>; 121def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", 122 [(set i32:$dst, (sext_inreg i32:$src0, i16))] 123>; 124 125////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 126////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 127////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 128////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 129def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 130def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 131def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 132def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 133 134let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 135 136def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 137def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 138def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 139def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 140def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 141def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 142def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 143def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 144 145} // End hasSideEffects = 1 146 147def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 148def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 149def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 150def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 151def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 152def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 153//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 154def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 155def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 156def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 157 158//===----------------------------------------------------------------------===// 159// SOP2 Instructions 160//===----------------------------------------------------------------------===// 161 162let Defs = [SCC] in { // Carry out goes to SCC 163let isCommutable = 1 in { 164def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 165def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", 166 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] 167>; 168} // End isCommutable = 1 169 170def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 171def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", 172 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] 173>; 174 175let Uses = [SCC] in { // Carry in comes from SCC 176let isCommutable = 1 in { 177def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", 178 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 179} // End isCommutable = 1 180 181def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", 182 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 183} // End Uses = [SCC] 184} // End Defs = [SCC] 185 186def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", 187 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] 188>; 189def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", 190 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] 191>; 192def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", 193 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] 194>; 195def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", 196 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] 197>; 198 199def S_CSELECT_B32 : SOP2 < 200 0x0000000a, (outs SReg_32:$dst), 201 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 202 [] 203>; 204 205def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 206 207def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", 208 [(set i32:$dst, (and i32:$src0, i32:$src1))] 209>; 210 211def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 212 [(set i64:$dst, (and i64:$src0, i64:$src1))] 213>; 214 215def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", 216 [(set i32:$dst, (or i32:$src0, i32:$src1))] 217>; 218 219def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", 220 [(set i64:$dst, (or i64:$src0, i64:$src1))] 221>; 222 223def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", 224 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 225>; 226 227def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", 228 [(set i64:$dst, (xor i64:$src0, i64:$src1))] 229>; 230def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 231def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 232def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 233def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 234def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 235def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 236def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 237def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 238def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 239def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 240 241// Use added complexity so these patterns are preferred to the VALU patterns. 242let AddedComplexity = 1 in { 243 244def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", 245 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 246>; 247def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64", 248 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 249>; 250def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", 251 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 252>; 253def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64", 254 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 255>; 256def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", 257 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 258>; 259def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64", 260 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 261>; 262 263} // End AddedComplexity = 1 264 265def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 266def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 267def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 268def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 269def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 270def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 271def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 272//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 273def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 274 275//===----------------------------------------------------------------------===// 276// SOPC Instructions 277//===----------------------------------------------------------------------===// 278 279def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">; 280def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">; 281def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">; 282def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">; 283def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">; 284def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">; 285def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">; 286def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">; 287def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">; 288def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">; 289def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">; 290def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">; 291////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 292////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 293////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 294////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 295//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 296 297//===----------------------------------------------------------------------===// 298// SOPK Instructions 299//===----------------------------------------------------------------------===// 300 301def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 302def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 303 304/* 305This instruction is disabled for now until we can figure out how to teach 306the instruction selector to correctly use the S_CMP* vs V_CMP* 307instructions. 308 309When this instruction is enabled the code generator sometimes produces this 310invalid sequence: 311 312SCC = S_CMPK_EQ_I32 SGPR0, imm 313VCC = COPY SCC 314VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 315 316def S_CMPK_EQ_I32 : SOPK < 317 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 318 "S_CMPK_EQ_I32", 319 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 320>; 321*/ 322 323let isCompare = 1 in { 324def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 325def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 326def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 327def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 328def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 329def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 330def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 331def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 332def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 333def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 334def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 335} // End isCompare = 1 336 337let Defs = [SCC], isCommutable = 1 in { 338 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 339 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 340} 341 342//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 343def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 344def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 345def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 346//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 347//def EXP : EXP_ <0x00000000, "EXP", []>; 348 349} // End let OtherPredicates = [isCFDepth0] 350 351//===----------------------------------------------------------------------===// 352// SOPP Instructions 353//===----------------------------------------------------------------------===// 354 355def S_NOP : SOPP <0x00000000, (ins i16imm:$SIMM16), "S_NOP $SIMM16", []>; 356 357let isTerminator = 1 in { 358 359def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 360 [(IL_retflag)]> { 361 let SIMM16 = 0; 362 let isBarrier = 1; 363 let hasCtrlDep = 1; 364} 365 366let isBranch = 1 in { 367def S_BRANCH : SOPP < 368 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 369 [(br bb:$target)]> { 370 let isBarrier = 1; 371} 372 373let DisableEncoding = "$scc" in { 374def S_CBRANCH_SCC0 : SOPP < 375 0x00000004, (ins brtarget:$target, SCCReg:$scc), 376 "S_CBRANCH_SCC0 $target", [] 377>; 378def S_CBRANCH_SCC1 : SOPP < 379 0x00000005, (ins brtarget:$target, SCCReg:$scc), 380 "S_CBRANCH_SCC1 $target", 381 [] 382>; 383} // End DisableEncoding = "$scc" 384 385def S_CBRANCH_VCCZ : SOPP < 386 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 387 "S_CBRANCH_VCCZ $target", 388 [] 389>; 390def S_CBRANCH_VCCNZ : SOPP < 391 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 392 "S_CBRANCH_VCCNZ $target", 393 [] 394>; 395 396let DisableEncoding = "$exec" in { 397def S_CBRANCH_EXECZ : SOPP < 398 0x00000008, (ins brtarget:$target, EXECReg:$exec), 399 "S_CBRANCH_EXECZ $target", 400 [] 401>; 402def S_CBRANCH_EXECNZ : SOPP < 403 0x00000009, (ins brtarget:$target, EXECReg:$exec), 404 "S_CBRANCH_EXECNZ $target", 405 [] 406>; 407} // End DisableEncoding = "$exec" 408 409 410} // End isBranch = 1 411} // End isTerminator = 1 412 413let hasSideEffects = 1 in { 414def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", 415 [(int_AMDGPU_barrier_local)] 416> { 417 let SIMM16 = 0; 418 let isBarrier = 1; 419 let hasCtrlDep = 1; 420 let mayLoad = 1; 421 let mayStore = 1; 422} 423 424def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16", 425 [] 426>; 427//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 428//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 429//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 430 431let Uses = [EXEC] in { 432 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16", 433 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)] 434 > { 435 let DisableEncoding = "$m0"; 436 } 437} // End Uses = [EXEC] 438 439//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 440//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 441//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 442//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 443//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 444//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 445} // End hasSideEffects 446 447//===----------------------------------------------------------------------===// 448// VOPC Instructions 449//===----------------------------------------------------------------------===// 450 451let isCompare = 1 in { 452 453defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 454defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>; 455defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>; 456defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>; 457defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>; 458defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">; 459defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>; 460defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>; 461defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>; 462defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 463defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 464defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 465defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 466defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>; 467defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 468defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 469 470let hasSideEffects = 1, Defs = [EXEC] in { 471 472defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 473defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 474defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 475defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 476defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 477defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 478defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 479defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 480defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 481defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 482defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 483defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 484defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 485defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 486defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 487defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 488 489} // End hasSideEffects = 1, Defs = [EXEC] 490 491defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 492defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>; 493defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>; 494defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>; 495defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>; 496defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 497defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>; 498defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>; 499defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>; 500defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 501defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 502defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 503defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 504defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>; 505defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 506defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 507 508let hasSideEffects = 1, Defs = [EXEC] in { 509 510defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 511defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 512defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 513defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 514defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 515defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 516defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 517defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 518defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 519defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 520defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 521defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 522defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 523defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 524defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 525defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 526 527} // End hasSideEffects = 1, Defs = [EXEC] 528 529defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 530defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 531defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 532defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 533defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 534defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 535defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 536defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 537defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 538defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 539defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 540defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 541defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 542defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 543defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 544defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 545 546let hasSideEffects = 1, Defs = [EXEC] in { 547 548defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 549defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 550defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 551defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 552defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 553defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 554defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 555defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 556defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 557defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 558defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 559defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 560defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 561defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 562defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 563defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 564 565} // End hasSideEffects = 1, Defs = [EXEC] 566 567defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 568defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 569defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 570defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 571defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 572defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 573defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 574defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 575defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 576defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 577defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 578defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 579defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 580defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 581defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 582defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 583 584let hasSideEffects = 1, Defs = [EXEC] in { 585 586defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 587defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 588defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 589defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 590defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 591defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 592defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 593defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 594defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 595defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 596defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 597defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 598defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 599defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 600defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 601defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 602 603} // End hasSideEffects = 1, Defs = [EXEC] 604 605defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 606defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>; 607defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 608defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>; 609defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>; 610defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 611defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>; 612defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 613 614let hasSideEffects = 1, Defs = [EXEC] in { 615 616defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 617defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 618defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 619defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 620defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 621defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 622defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 623defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 624 625} // End hasSideEffects = 1, Defs = [EXEC] 626 627defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 628defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>; 629defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>; 630defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>; 631defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>; 632defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>; 633defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>; 634defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 635 636let hasSideEffects = 1, Defs = [EXEC] in { 637 638defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 639defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 640defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 641defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 642defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 643defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 644defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 645defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 646 647} // End hasSideEffects = 1, Defs = [EXEC] 648 649defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 650defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>; 651defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>; 652defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>; 653defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>; 654defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>; 655defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>; 656defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 657 658let hasSideEffects = 1, Defs = [EXEC] in { 659 660defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 661defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 662defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 663defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 664defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 665defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 666defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 667defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 668 669} // End hasSideEffects = 1, Defs = [EXEC] 670 671defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 672defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>; 673defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>; 674defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>; 675defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>; 676defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>; 677defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>; 678defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 679 680let hasSideEffects = 1, Defs = [EXEC] in { 681 682defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 683defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 684defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 685defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 686defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 687defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 688defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 689defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 690 691} // End hasSideEffects = 1, Defs = [EXEC] 692 693defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 694 695let hasSideEffects = 1, Defs = [EXEC] in { 696defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 697} // End hasSideEffects = 1, Defs = [EXEC] 698 699defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 700 701let hasSideEffects = 1, Defs = [EXEC] in { 702defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 703} // End hasSideEffects = 1, Defs = [EXEC] 704 705} // End isCompare = 1 706 707//===----------------------------------------------------------------------===// 708// DS Instructions 709//===----------------------------------------------------------------------===// 710 711def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>; 712def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>; 713def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; 714def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>; 715def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>; 716def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>; 717 718def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>; 719def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>; 720def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>; 721def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>; 722def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; 723def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>; 724 725// 2 forms. 726def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>; 727def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>; 728 729def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>; 730def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>; 731 732// TODO: DS_READ2ST64_B32, DS_READ2ST64_B64, 733// DS_WRITE2ST64_B32, DS_WRITE2ST64_B64 734 735//===----------------------------------------------------------------------===// 736// MUBUF Instructions 737//===----------------------------------------------------------------------===// 738 739//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 740//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 741//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 742defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 743//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 744//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 745//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 746//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 747defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; 748defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>; 749defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>; 750defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>; 751defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 752defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 753defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 754 755def BUFFER_STORE_BYTE : MUBUF_Store_Helper < 756 0x00000018, "BUFFER_STORE_BYTE", VReg_32 757>; 758 759def BUFFER_STORE_SHORT : MUBUF_Store_Helper < 760 0x0000001a, "BUFFER_STORE_SHORT", VReg_32 761>; 762 763def BUFFER_STORE_DWORD : MUBUF_Store_Helper < 764 0x0000001c, "BUFFER_STORE_DWORD", VReg_32 765>; 766 767def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 768 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64 769>; 770 771def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 772 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128 773>; 774//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 775//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 776//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 777//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 778//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 779//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 780//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 781//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 782//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 783//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 784//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 785//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 786//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 787//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 788//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 789//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 790//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 791//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 792//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 793//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 794//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 795//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 796//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 797//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 798//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 799//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 800//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 801//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 802//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 803//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 804//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 805//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 806//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 807//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 808//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 809//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 810 811//===----------------------------------------------------------------------===// 812// MTBUF Instructions 813//===----------------------------------------------------------------------===// 814 815//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 816//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 817//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 818def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 819def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; 820def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; 821def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; 822def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; 823 824//===----------------------------------------------------------------------===// 825// MIMG Instructions 826//===----------------------------------------------------------------------===// 827 828defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">; 829defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">; 830//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 831//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 832//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 833//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 834//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 835//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 836//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 837//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 838defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">; 839//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 840//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 841//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 842//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 843//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 844//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 845//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 846//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 847//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 848//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 849//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 850//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 851//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 852//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 853//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 854//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 855//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 856defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; 857//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 858defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; 859//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 860defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; 861defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; 862//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 863//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 864defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; 865//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 866defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; 867//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 868defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; 869defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; 870//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 871//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 872//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 873//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 874//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 875//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 876//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 877//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 878//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 879//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 880//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 881//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 882//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 883//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 884//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 885//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 886//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 887//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 888//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 889//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 890//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 891//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 892//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 893//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 894//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 895//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 896//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 897//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 898//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 899//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 900//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 901//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 902//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 903//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 904//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 905//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 906//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 907//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 908//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 909//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 910//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 911//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 912//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 913//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 914//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 915//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 916//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 917//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 918//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 919//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 920//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 921//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 922//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 923 924//===----------------------------------------------------------------------===// 925// VOP1 Instructions 926//===----------------------------------------------------------------------===// 927 928//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 929 930let neverHasSideEffects = 1, isMoveImm = 1 in { 931defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 932} // End neverHasSideEffects = 1, isMoveImm = 1 933 934let Uses = [EXEC] in { 935 936def V_READFIRSTLANE_B32 : VOP1 < 937 0x00000002, 938 (outs SReg_32:$vdst), 939 (ins VReg_32:$src0), 940 "V_READFIRSTLANE_B32 $vdst, $src0", 941 [] 942>; 943 944} 945 946defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", 947 [(set i32:$dst, (fp_to_sint f64:$src0))] 948>; 949defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32", 950 [(set f64:$dst, (sint_to_fp i32:$src0))] 951>; 952defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 953 [(set f32:$dst, (sint_to_fp i32:$src0))] 954>; 955defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", 956 [(set f32:$dst, (uint_to_fp i32:$src0))] 957>; 958defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", 959 [(set i32:$dst, (fp_to_uint f32:$src0))] 960>; 961defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 962 [(set i32:$dst, (fp_to_sint f32:$src0))] 963>; 964defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 965////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 966//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 967//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 968//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 969//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 970defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64", 971 [(set f32:$dst, (fround f64:$src0))] 972>; 973defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32", 974 [(set f64:$dst, (fextend f32:$src0))] 975>; 976//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 977//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 978//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 979//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 980defm V_CVT_U32_F64 : VOP1_32_64 <0x00000015, "V_CVT_U32_F64", 981 [(set i32:$dst, (fp_to_uint f64:$src0))] 982>; 983defm V_CVT_F64_U32 : VOP1_64_32 <0x00000016, "V_CVT_F64_U32", 984 [(set f64:$dst, (uint_to_fp i32:$src0))] 985>; 986 987defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 988 [(set f32:$dst, (AMDGPUfract f32:$src0))] 989>; 990defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", 991 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] 992>; 993defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 994 [(set f32:$dst, (fceil f32:$src0))] 995>; 996defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 997 [(set f32:$dst, (frint f32:$src0))] 998>; 999defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 1000 [(set f32:$dst, (ffloor f32:$src0))] 1001>; 1002defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 1003 [(set f32:$dst, (fexp2 f32:$src0))] 1004>; 1005defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 1006defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 1007 [(set f32:$dst, (flog2 f32:$src0))] 1008>; 1009defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 1010defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 1011defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 1012 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 1013>; 1014defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 1015defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 1016defm V_RSQ_LEGACY_F32 : VOP1_32 < 1017 0x0000002d, "V_RSQ_LEGACY_F32", 1018 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] 1019>; 1020defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 1021defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", 1022 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))] 1023>; 1024defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 1025defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 1026defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 1027defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", 1028 [(set f32:$dst, (fsqrt f32:$src0))] 1029>; 1030defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", 1031 [(set f64:$dst, (fsqrt f64:$src0))] 1032>; 1033defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 1034defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 1035defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 1036defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 1037defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 1038defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 1039defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 1040//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 1041defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 1042defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 1043//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 1044defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 1045//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 1046defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 1047defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 1048defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 1049 1050 1051//===----------------------------------------------------------------------===// 1052// VINTRP Instructions 1053//===----------------------------------------------------------------------===// 1054 1055def V_INTERP_P1_F32 : VINTRP < 1056 0x00000000, 1057 (outs VReg_32:$dst), 1058 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 1059 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 1060 []> { 1061 let DisableEncoding = "$m0"; 1062} 1063 1064def V_INTERP_P2_F32 : VINTRP < 1065 0x00000001, 1066 (outs VReg_32:$dst), 1067 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 1068 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 1069 []> { 1070 1071 let Constraints = "$src0 = $dst"; 1072 let DisableEncoding = "$src0,$m0"; 1073 1074} 1075 1076def V_INTERP_MOV_F32 : VINTRP < 1077 0x00000002, 1078 (outs VReg_32:$dst), 1079 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 1080 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 1081 []> { 1082 let DisableEncoding = "$m0"; 1083} 1084 1085//===----------------------------------------------------------------------===// 1086// VOP2 Instructions 1087//===----------------------------------------------------------------------===// 1088 1089def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 1090 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 1091 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 1092 [] 1093>{ 1094 let DisableEncoding = "$vcc"; 1095} 1096 1097def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 1098 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 1099 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 1100 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 1101 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] 1102> { 1103 let src0_modifiers = 0; 1104 let src1_modifiers = 0; 1105 let src2_modifiers = 0; 1106} 1107 1108def V_READLANE_B32 : VOP2 < 1109 0x00000001, 1110 (outs SReg_32:$vdst), 1111 (ins VReg_32:$src0, SSrc_32:$vsrc1), 1112 "V_READLANE_B32 $vdst, $src0, $vsrc1", 1113 [] 1114>; 1115 1116def V_WRITELANE_B32 : VOP2 < 1117 0x00000002, 1118 (outs VReg_32:$vdst), 1119 (ins SReg_32:$src0, SSrc_32:$vsrc1), 1120 "V_WRITELANE_B32 $vdst, $src0, $vsrc1", 1121 [] 1122>; 1123 1124let isCommutable = 1 in { 1125defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 1126 [(set f32:$dst, (fadd f32:$src0, f32:$src1))] 1127>; 1128 1129defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 1130 [(set f32:$dst, (fsub f32:$src0, f32:$src1))] 1131>; 1132defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 1133} // End isCommutable = 1 1134 1135defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 1136 1137let isCommutable = 1 in { 1138 1139defm V_MUL_LEGACY_F32 : VOP2_32 < 1140 0x00000007, "V_MUL_LEGACY_F32", 1141 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] 1142>; 1143 1144defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 1145 [(set f32:$dst, (fmul f32:$src0, f32:$src1))] 1146>; 1147 1148 1149defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", 1150 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))] 1151>; 1152//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 1153defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", 1154 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))] 1155>; 1156//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 1157 1158 1159defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 1160 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] 1161>; 1162 1163defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 1164 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] 1165>; 1166 1167defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 1168defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 1169defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", 1170 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>; 1171defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", 1172 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>; 1173defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", 1174 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>; 1175defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", 1176 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>; 1177 1178defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", 1179 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 1180>; 1181 1182defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 1183 1184defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", 1185 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 1186>; 1187defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 1188 1189let hasPostISelHook = 1 in { 1190 1191defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 1192 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 1193>; 1194 1195} 1196defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 1197 1198defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 1199 [(set i32:$dst, (and i32:$src0, i32:$src1))]>; 1200defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 1201 [(set i32:$dst, (or i32:$src0, i32:$src1))] 1202>; 1203defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 1204 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 1205>; 1206 1207} // End isCommutable = 1 1208 1209defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", 1210 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>; 1211defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 1212defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 1213defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 1214//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 1215defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 1216defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 1217 1218let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 1219// No patterns so that the scalar instructions are always selected. 1220// The scalar versions will be replaced with vector when needed later. 1221defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", 1222 [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>; 1223defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", 1224 [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>; 1225defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32, 1226 "V_SUB_I32">; 1227 1228let Uses = [VCC] in { // Carry-in comes from VCC 1229defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", 1230 [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>; 1231defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", 1232 [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>; 1233defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32, 1234 "V_SUBB_U32">; 1235} // End Uses = [VCC] 1236} // End isCommutable = 1, Defs = [VCC] 1237 1238defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 1239////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 1240////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 1241////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 1242defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 1243 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] 1244>; 1245////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 1246////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 1247 1248//===----------------------------------------------------------------------===// 1249// VOP3 Instructions 1250//===----------------------------------------------------------------------===// 1251 1252let neverHasSideEffects = 1 in { 1253 1254defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 1255defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", 1256 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))] 1257>; 1258defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", 1259 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))] 1260>; 1261defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", 1262 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))] 1263>; 1264 1265} // End neverHasSideEffects 1266 1267defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 1268defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 1269defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 1270defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 1271 1272let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in { 1273defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", 1274 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>; 1275defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", 1276 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>; 1277} 1278 1279defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", 1280 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>; 1281defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", 1282 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))] 1283>; 1284def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", 1285 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 1286>; 1287//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 1288defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 1289 1290defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 1291defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 1292////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 1293////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 1294////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 1295////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 1296////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 1297////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 1298////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 1299////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 1300////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 1301//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 1302//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 1303//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 1304defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 1305////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 1306defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 1307def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 1308 1309def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64", 1310 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1311>; 1312def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64", 1313 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1314>; 1315def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64", 1316 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1317>; 1318 1319let isCommutable = 1 in { 1320 1321def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 1322def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 1323def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 1324def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 1325 1326} // isCommutable = 1 1327 1328def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 1329 1330let isCommutable = 1 in { 1331 1332defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 1333defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 1334defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 1335defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 1336 1337} // isCommutable = 1 1338 1339defm V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1340def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1341defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1342def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1343//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1344//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1345//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1346def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1347 1348//===----------------------------------------------------------------------===// 1349// Pseudo Instructions 1350//===----------------------------------------------------------------------===// 1351 1352let isCodeGenOnly = 1, isPseudo = 1 in { 1353 1354def V_MOV_I1 : InstSI < 1355 (outs VReg_1:$dst), 1356 (ins i1imm:$src), 1357 "", [(set i1:$dst, (imm:$src))] 1358>; 1359 1360def V_AND_I1 : InstSI < 1361 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "", 1362 [(set i1:$dst, (and i1:$src0, i1:$src1))] 1363>; 1364 1365def V_OR_I1 : InstSI < 1366 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "", 1367 [(set i1:$dst, (or i1:$src0, i1:$src1))] 1368>; 1369 1370// SI pseudo instructions. These are used by the CFG structurizer pass 1371// and should be lowered to ISA instructions prior to codegen. 1372 1373let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1374 Uses = [EXEC], Defs = [EXEC] in { 1375 1376let isBranch = 1, isTerminator = 1 in { 1377 1378def SI_IF: InstSI < 1379 (outs SReg_64:$dst), 1380 (ins SReg_64:$vcc, brtarget:$target), 1381 "", 1382 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1383>; 1384 1385def SI_ELSE : InstSI < 1386 (outs SReg_64:$dst), 1387 (ins SReg_64:$src, brtarget:$target), 1388 "", 1389 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))] 1390> { 1391 let Constraints = "$src = $dst"; 1392} 1393 1394def SI_LOOP : InstSI < 1395 (outs), 1396 (ins SReg_64:$saved, brtarget:$target), 1397 "SI_LOOP $saved, $target", 1398 [(int_SI_loop i64:$saved, bb:$target)] 1399>; 1400 1401} // end isBranch = 1, isTerminator = 1 1402 1403def SI_BREAK : InstSI < 1404 (outs SReg_64:$dst), 1405 (ins SReg_64:$src), 1406 "SI_ELSE $dst, $src", 1407 [(set i64:$dst, (int_SI_break i64:$src))] 1408>; 1409 1410def SI_IF_BREAK : InstSI < 1411 (outs SReg_64:$dst), 1412 (ins SReg_64:$vcc, SReg_64:$src), 1413 "SI_IF_BREAK $dst, $vcc, $src", 1414 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1415>; 1416 1417def SI_ELSE_BREAK : InstSI < 1418 (outs SReg_64:$dst), 1419 (ins SReg_64:$src0, SReg_64:$src1), 1420 "SI_ELSE_BREAK $dst, $src0, $src1", 1421 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1422>; 1423 1424def SI_END_CF : InstSI < 1425 (outs), 1426 (ins SReg_64:$saved), 1427 "SI_END_CF $saved", 1428 [(int_SI_end_cf i64:$saved)] 1429>; 1430 1431def SI_KILL : InstSI < 1432 (outs), 1433 (ins VSrc_32:$src), 1434 "SI_KILL $src", 1435 [(int_AMDGPU_kill f32:$src)] 1436>; 1437 1438} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1439 // Uses = [EXEC], Defs = [EXEC] 1440 1441let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1442 1443//defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>; 1444 1445let UseNamedOperandTable = 1 in { 1446 1447def SI_RegisterLoad : InstSI < 1448 (outs VReg_32:$dst, SReg_64:$temp), 1449 (ins FRAMEri32:$addr, i32imm:$chan), 1450 "", [] 1451> { 1452 let isRegisterLoad = 1; 1453 let mayLoad = 1; 1454} 1455 1456class SIRegStore<dag outs> : InstSI < 1457 outs, 1458 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan), 1459 "", [] 1460> { 1461 let isRegisterStore = 1; 1462 let mayStore = 1; 1463} 1464 1465let usesCustomInserter = 1 in { 1466def SI_RegisterStorePseudo : SIRegStore<(outs)>; 1467} // End usesCustomInserter = 1 1468def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>; 1469 1470 1471} // End UseNamedOperandTable = 1 1472 1473def SI_INDIRECT_SRC : InstSI < 1474 (outs VReg_32:$dst, SReg_64:$temp), 1475 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1476 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1477 [] 1478>; 1479 1480class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1481 (outs rc:$dst, SReg_64:$temp), 1482 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1483 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1484 [] 1485> { 1486 let Constraints = "$src = $dst"; 1487} 1488 1489def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>; 1490def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1491def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1492def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1493def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1494 1495} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1496 1497let usesCustomInserter = 1 in { 1498 1499// This pseudo instruction takes a pointer as input and outputs a resource 1500// constant that can be used with the ADDR64 MUBUF instructions. 1501def SI_ADDR64_RSRC : InstSI < 1502 (outs SReg_128:$srsrc), 1503 (ins SReg_64:$ptr), 1504 "", [] 1505>; 1506 1507def V_SUB_F64 : InstSI < 1508 (outs VReg_64:$dst), 1509 (ins VReg_64:$src0, VReg_64:$src1), 1510 "V_SUB_F64 $dst, $src0, $src1", 1511 [] 1512>; 1513 1514} // end usesCustomInserter 1515 1516multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> { 1517 1518 def _SAVE : InstSI < 1519 (outs VReg_32:$dst), 1520 (ins sgpr_class:$src, i32imm:$frame_idx), 1521 "", [] 1522 >; 1523 1524 def _RESTORE : InstSI < 1525 (outs sgpr_class:$dst), 1526 (ins VReg_32:$src, i32imm:$frame_idx), 1527 "", [] 1528 >; 1529 1530} 1531 1532defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>; 1533defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>; 1534defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>; 1535defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>; 1536 1537} // end IsCodeGenOnly, isPseudo 1538 1539} // end SubtargetPredicate = SI 1540 1541let Predicates = [isSI] in { 1542 1543def : Pat< 1544 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 1545 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) 1546>; 1547 1548def : Pat < 1549 (int_AMDGPU_kilp), 1550 (SI_KILL 0xbf800000) 1551>; 1552 1553/* int_SI_vs_load_input */ 1554def : Pat< 1555 (SIload_input v4i32:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr), 1556 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0) 1557>; 1558 1559/* int_SI_export */ 1560def : Pat < 1561 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1562 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 1563 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1564 $src0, $src1, $src2, $src3) 1565>; 1566 1567def : Pat < 1568 (f64 (fsub f64:$src0, f64:$src1)), 1569 (V_SUB_F64 $src0, $src1) 1570>; 1571 1572//===----------------------------------------------------------------------===// 1573// SMRD Patterns 1574//===----------------------------------------------------------------------===// 1575 1576multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1577 1578 // 1. Offset as 8bit DWORD immediate 1579 def : Pat < 1580 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))), 1581 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset))) 1582 >; 1583 1584 // 2. Offset loaded in an 32bit SGPR 1585 def : Pat < 1586 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))), 1587 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset))))) 1588 >; 1589 1590 // 3. No offset at all 1591 def : Pat < 1592 (constant_load i64:$sbase), 1593 (vt (Instr_IMM $sbase, 0)) 1594 >; 1595} 1596 1597defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1598defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1599defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>; 1600defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>; 1601defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>; 1602defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1603defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>; 1604defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>; 1605 1606// 1. Offset as 8bit DWORD immediate 1607def : Pat < 1608 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset), 1609 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset)) 1610>; 1611 1612// 2. Offset loaded in an 32bit SGPR 1613def : Pat < 1614 (SIload_constant v4i32:$sbase, imm:$offset), 1615 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) 1616>; 1617 1618//===----------------------------------------------------------------------===// 1619// SOP2 Patterns 1620//===----------------------------------------------------------------------===// 1621 1622def : Pat < 1623 (i1 (xor i1:$src0, i1:$src1)), 1624 (S_XOR_B64 $src0, $src1) 1625>; 1626 1627//===----------------------------------------------------------------------===// 1628// VOP2 Patterns 1629//===----------------------------------------------------------------------===// 1630 1631def : Pat < 1632 (or i64:$src0, i64:$src1), 1633 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1634 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0), 1635 (EXTRACT_SUBREG i64:$src1, sub0)), sub0), 1636 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1), 1637 (EXTRACT_SUBREG i64:$src1, sub1)), sub1) 1638>; 1639 1640class SextInReg <ValueType vt, int ShiftAmt> : Pat < 1641 (sext_inreg i32:$src0, vt), 1642 (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0)) 1643>; 1644 1645def : SextInReg <i8, 24>; 1646def : SextInReg <i16, 16>; 1647 1648/********** ======================= **********/ 1649/********** Image sampling patterns **********/ 1650/********** ======================= **********/ 1651 1652/* SIsample for simple 1D texture lookup */ 1653def : Pat < 1654 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm), 1655 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1656>; 1657 1658class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1659 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm), 1660 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1661>; 1662 1663class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1664 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT), 1665 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1666>; 1667 1668class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1669 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY), 1670 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1671>; 1672 1673class SampleShadowPattern<SDNode name, MIMG opcode, 1674 ValueType vt> : Pat < 1675 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW), 1676 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1677>; 1678 1679class SampleShadowArrayPattern<SDNode name, MIMG opcode, 1680 ValueType vt> : Pat < 1681 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY), 1682 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1683>; 1684 1685/* SIsample* for texture lookups consuming more address parameters */ 1686multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 1687 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 1688MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 1689 def : SamplePattern <SIsample, sample, addr_type>; 1690 def : SampleRectPattern <SIsample, sample, addr_type>; 1691 def : SampleArrayPattern <SIsample, sample, addr_type>; 1692 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 1693 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 1694 1695 def : SamplePattern <SIsamplel, sample_l, addr_type>; 1696 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 1697 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 1698 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 1699 1700 def : SamplePattern <SIsampleb, sample_b, addr_type>; 1701 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 1702 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 1703 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 1704 1705 def : SamplePattern <SIsampled, sample_d, addr_type>; 1706 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 1707 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 1708 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 1709} 1710 1711defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 1712 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 1713 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 1714 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 1715 v2i32>; 1716defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 1717 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 1718 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 1719 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 1720 v4i32>; 1721defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 1722 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 1723 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 1724 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 1725 v8i32>; 1726defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 1727 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 1728 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 1729 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 1730 v16i32>; 1731 1732/* int_SI_imageload for texture fetches consuming varying address parameters */ 1733class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1734 (name addr_type:$addr, v32i8:$rsrc, imm), 1735 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1736>; 1737 1738class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1739 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 1740 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1741>; 1742 1743class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1744 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA), 1745 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1746>; 1747 1748class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1749 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA), 1750 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1751>; 1752 1753multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> { 1754 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>; 1755 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>; 1756} 1757 1758multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> { 1759 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>; 1760 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>; 1761} 1762 1763defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>; 1764defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>; 1765 1766defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>; 1767defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>; 1768 1769/* Image resource information */ 1770def : Pat < 1771 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 1772 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1773>; 1774 1775def : Pat < 1776 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 1777 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1778>; 1779 1780def : Pat < 1781 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA), 1782 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1783>; 1784 1785/********** ============================================ **********/ 1786/********** Extraction, Insertion, Building and Casting **********/ 1787/********** ============================================ **********/ 1788 1789foreach Index = 0-2 in { 1790 def Extract_Element_v2i32_#Index : Extract_Element < 1791 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1792 >; 1793 def Insert_Element_v2i32_#Index : Insert_Element < 1794 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1795 >; 1796 1797 def Extract_Element_v2f32_#Index : Extract_Element < 1798 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1799 >; 1800 def Insert_Element_v2f32_#Index : Insert_Element < 1801 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1802 >; 1803} 1804 1805foreach Index = 0-3 in { 1806 def Extract_Element_v4i32_#Index : Extract_Element < 1807 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1808 >; 1809 def Insert_Element_v4i32_#Index : Insert_Element < 1810 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1811 >; 1812 1813 def Extract_Element_v4f32_#Index : Extract_Element < 1814 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1815 >; 1816 def Insert_Element_v4f32_#Index : Insert_Element < 1817 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1818 >; 1819} 1820 1821foreach Index = 0-7 in { 1822 def Extract_Element_v8i32_#Index : Extract_Element < 1823 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1824 >; 1825 def Insert_Element_v8i32_#Index : Insert_Element < 1826 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1827 >; 1828 1829 def Extract_Element_v8f32_#Index : Extract_Element < 1830 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1831 >; 1832 def Insert_Element_v8f32_#Index : Insert_Element < 1833 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1834 >; 1835} 1836 1837foreach Index = 0-15 in { 1838 def Extract_Element_v16i32_#Index : Extract_Element < 1839 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1840 >; 1841 def Insert_Element_v16i32_#Index : Insert_Element < 1842 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1843 >; 1844 1845 def Extract_Element_v16f32_#Index : Extract_Element < 1846 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1847 >; 1848 def Insert_Element_v16f32_#Index : Insert_Element < 1849 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1850 >; 1851} 1852 1853def : BitConvert <i32, f32, SReg_32>; 1854def : BitConvert <i32, f32, VReg_32>; 1855 1856def : BitConvert <f32, i32, SReg_32>; 1857def : BitConvert <f32, i32, VReg_32>; 1858 1859def : BitConvert <i64, f64, VReg_64>; 1860 1861def : BitConvert <f64, i64, VReg_64>; 1862 1863def : BitConvert <v2f32, v2i32, VReg_64>; 1864def : BitConvert <v2i32, v2f32, VReg_64>; 1865def : BitConvert <v2i32, i64, VReg_64>; 1866def : BitConvert <i64, v2i32, VReg_64>; 1867 1868def : BitConvert <v4f32, v4i32, VReg_128>; 1869def : BitConvert <v4i32, v4f32, VReg_128>; 1870 1871def : BitConvert <v8f32, v8i32, SReg_256>; 1872def : BitConvert <v8i32, v8f32, SReg_256>; 1873def : BitConvert <v8i32, v32i8, SReg_256>; 1874def : BitConvert <v32i8, v8i32, SReg_256>; 1875def : BitConvert <v8i32, v32i8, VReg_256>; 1876def : BitConvert <v8i32, v8f32, VReg_256>; 1877def : BitConvert <v8f32, v8i32, VReg_256>; 1878def : BitConvert <v32i8, v8i32, VReg_256>; 1879 1880def : BitConvert <v16i32, v16f32, VReg_512>; 1881def : BitConvert <v16f32, v16i32, VReg_512>; 1882 1883/********** =================== **********/ 1884/********** Src & Dst modifiers **********/ 1885/********** =================== **********/ 1886 1887def FCLAMP_SI : AMDGPUShaderInst < 1888 (outs VReg_32:$dst), 1889 (ins VSrc_32:$src0), 1890 "FCLAMP_SI $dst, $src0", 1891 [] 1892> { 1893 let usesCustomInserter = 1; 1894} 1895 1896def : Pat < 1897 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1898 (FCLAMP_SI f32:$src) 1899>; 1900 1901/********** ================================ **********/ 1902/********** Floating point absolute/negative **********/ 1903/********** ================================ **********/ 1904 1905// Manipulate the sign bit directly, as e.g. using the source negation modifier 1906// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0, 1907// breaking the piglit *s-floatBitsToInt-neg* tests 1908 1909// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly 1910// removing these patterns 1911 1912def : Pat < 1913 (fneg (fabs f32:$src)), 1914 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */ 1915>; 1916 1917def FABS_SI : AMDGPUShaderInst < 1918 (outs VReg_32:$dst), 1919 (ins VSrc_32:$src0), 1920 "FABS_SI $dst, $src0", 1921 [] 1922> { 1923 let usesCustomInserter = 1; 1924} 1925 1926def : Pat < 1927 (fabs f32:$src), 1928 (FABS_SI f32:$src) 1929>; 1930 1931def FNEG_SI : AMDGPUShaderInst < 1932 (outs VReg_32:$dst), 1933 (ins VSrc_32:$src0), 1934 "FNEG_SI $dst, $src0", 1935 [] 1936> { 1937 let usesCustomInserter = 1; 1938} 1939 1940def : Pat < 1941 (fneg f32:$src), 1942 (FNEG_SI f32:$src) 1943>; 1944 1945/********** ================== **********/ 1946/********** Immediate Patterns **********/ 1947/********** ================== **********/ 1948 1949def : Pat < 1950 (SGPRImm<(i32 imm)>:$imm), 1951 (S_MOV_B32 imm:$imm) 1952>; 1953 1954def : Pat < 1955 (SGPRImm<(f32 fpimm)>:$imm), 1956 (S_MOV_B32 fpimm:$imm) 1957>; 1958 1959def : Pat < 1960 (i32 imm:$imm), 1961 (V_MOV_B32_e32 imm:$imm) 1962>; 1963 1964def : Pat < 1965 (f32 fpimm:$imm), 1966 (V_MOV_B32_e32 fpimm:$imm) 1967>; 1968 1969def : Pat < 1970 (i64 InlineImm<i64>:$imm), 1971 (S_MOV_B64 InlineImm<i64>:$imm) 1972>; 1973 1974/********** ===================== **********/ 1975/********** Interpolation Paterns **********/ 1976/********** ===================== **********/ 1977 1978def : Pat < 1979 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params), 1980 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params) 1981>; 1982 1983def : Pat < 1984 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij), 1985 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0), 1986 imm:$attr_chan, imm:$attr, i32:$params), 1987 (EXTRACT_SUBREG $ij, sub1), 1988 imm:$attr_chan, imm:$attr, $params) 1989>; 1990 1991/********** ================== **********/ 1992/********** Intrinsic Patterns **********/ 1993/********** ================== **********/ 1994 1995/* llvm.AMDGPU.pow */ 1996def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 1997 1998def : Pat < 1999 (int_AMDGPU_div f32:$src0, f32:$src1), 2000 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 2001>; 2002 2003def : Pat< 2004 (fdiv f32:$src0, f32:$src1), 2005 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) 2006>; 2007 2008def : Pat< 2009 (fdiv f64:$src0, f64:$src1), 2010 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) 2011>; 2012 2013def : Pat < 2014 (fcos f32:$src0), 2015 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 2016>; 2017 2018def : Pat < 2019 (fsin f32:$src0), 2020 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 2021>; 2022 2023def : Pat < 2024 (int_AMDGPU_cube v4f32:$src), 2025 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 2026 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), 2027 (EXTRACT_SUBREG $src, sub1), 2028 (EXTRACT_SUBREG $src, sub2)), 2029 sub0), 2030 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), 2031 (EXTRACT_SUBREG $src, sub1), 2032 (EXTRACT_SUBREG $src, sub2)), 2033 sub1), 2034 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), 2035 (EXTRACT_SUBREG $src, sub1), 2036 (EXTRACT_SUBREG $src, sub2)), 2037 sub2), 2038 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), 2039 (EXTRACT_SUBREG $src, sub1), 2040 (EXTRACT_SUBREG $src, sub2)), 2041 sub3) 2042>; 2043 2044def : Pat < 2045 (i32 (sext i1:$src0)), 2046 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 2047>; 2048 2049class Ext32Pat <SDNode ext> : Pat < 2050 (i32 (ext i1:$src0)), 2051 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0) 2052>; 2053 2054def : Ext32Pat <zext>; 2055def : Ext32Pat <anyext>; 2056 2057// Offset in an 32Bit VGPR 2058def : Pat < 2059 (SIload_constant v4i32:$sbase, i32:$voff), 2060 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0) 2061>; 2062 2063// The multiplication scales from [0,1] to the unsigned integer range 2064def : Pat < 2065 (AMDGPUurecip i32:$src0), 2066 (V_CVT_U32_F32_e32 2067 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 2068 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 2069>; 2070 2071def : Pat < 2072 (int_SI_tid), 2073 (V_MBCNT_HI_U32_B32_e32 0xffffffff, 2074 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0)) 2075>; 2076 2077//===----------------------------------------------------------------------===// 2078// VOP3 Patterns 2079//===----------------------------------------------------------------------===// 2080 2081def : IMad24Pat<V_MAD_I32_I24>; 2082def : UMad24Pat<V_MAD_U32_U24>; 2083 2084def : Pat < 2085 (fadd f64:$src0, f64:$src1), 2086 (V_ADD_F64 $src0, $src1, (i64 0)) 2087>; 2088 2089def : Pat < 2090 (fmul f64:$src0, f64:$src1), 2091 (V_MUL_F64 $src0, $src1, (i64 0)) 2092>; 2093 2094def : Pat < 2095 (mul i32:$src0, i32:$src1), 2096 (V_MUL_LO_I32 $src0, $src1, (i32 0)) 2097>; 2098 2099def : Pat < 2100 (mulhu i32:$src0, i32:$src1), 2101 (V_MUL_HI_U32 $src0, $src1, (i32 0)) 2102>; 2103 2104def : Pat < 2105 (mulhs i32:$src0, i32:$src1), 2106 (V_MUL_HI_I32 $src0, $src1, (i32 0)) 2107>; 2108 2109defm : BFIPatterns <V_BFI_B32>; 2110def : ROTRPattern <V_ALIGNBIT_B32>; 2111 2112/********** ======================= **********/ 2113/********** Load/Store Patterns **********/ 2114/********** ======================= **********/ 2115 2116multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> { 2117 def : Pat < 2118 (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))), 2119 (inst (i1 0), $ptr, (as_i16imm $offset)) 2120 >; 2121 2122 def : Pat < 2123 (frag i32:$src0), 2124 (vt (inst 0, $src0, 0)) 2125 >; 2126} 2127 2128defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>; 2129defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>; 2130defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>; 2131defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>; 2132defm : DSReadPat <DS_READ_B32, i32, local_load>; 2133defm : DSReadPat <DS_READ_B64, i64, local_load>; 2134 2135multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> { 2136 def : Pat < 2137 (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))), 2138 (inst (i1 0), $ptr, $value, (as_i16imm $offset)) 2139 >; 2140 2141 def : Pat < 2142 (frag vt:$src1, i32:$src0), 2143 (inst 0, $src0, $src1, 0) 2144 >; 2145} 2146 2147defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>; 2148defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>; 2149defm : DSWritePat <DS_WRITE_B32, i32, local_store>; 2150defm : DSWritePat <DS_WRITE_B64, i64, local_store>; 2151 2152def : Pat <(atomic_load_add_local i32:$ptr, i32:$val), 2153 (DS_ADD_U32_RTN 0, $ptr, $val, 0)>; 2154 2155def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val), 2156 (DS_SUB_U32_RTN 0, $ptr, $val, 0)>; 2157 2158//===----------------------------------------------------------------------===// 2159// MUBUF Patterns 2160//===----------------------------------------------------------------------===// 2161 2162multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 2163 PatFrag global_ld, PatFrag constant_ld> { 2164 def : Pat < 2165 (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))), 2166 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset)) 2167 >; 2168 2169 def : Pat < 2170 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), 2171 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 2172 >; 2173 2174 def : Pat < 2175 (vt (global_ld i64:$ptr)), 2176 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 2177 >; 2178 2179 def : Pat < 2180 (vt (global_ld (add i64:$ptr, i64:$offset))), 2181 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 2182 >; 2183 2184 def : Pat < 2185 (vt (constant_ld (add i64:$ptr, i64:$offset))), 2186 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 2187 >; 2188} 2189 2190defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, 2191 sextloadi8_global, sextloadi8_constant>; 2192defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, 2193 az_extloadi8_global, az_extloadi8_constant>; 2194defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, 2195 sextloadi16_global, sextloadi16_constant>; 2196defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, 2197 az_extloadi16_global, az_extloadi16_constant>; 2198defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, 2199 global_load, constant_load>; 2200defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 2201 global_load, constant_load>; 2202defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 2203 az_extloadi32_global, az_extloadi32_constant>; 2204defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, 2205 global_load, constant_load>; 2206defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, 2207 global_load, constant_load>; 2208 2209multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> { 2210 2211 def : Pat < 2212 (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)), 2213 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset)) 2214 >; 2215 2216 def : Pat < 2217 (st vt:$value, (add i64:$ptr, IMM12bit:$offset)), 2218 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 2219 >; 2220 2221 def : Pat < 2222 (st vt:$value, i64:$ptr), 2223 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 2224 >; 2225 2226 def : Pat < 2227 (st vt:$value, (add i64:$ptr, i64:$offset)), 2228 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0) 2229 >; 2230} 2231 2232defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>; 2233defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>; 2234defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>; 2235defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>; 2236defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>; 2237defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>; 2238 2239// BUFFER_LOAD_DWORD*, addr64=0 2240multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen, 2241 MUBUF bothen> { 2242 2243 def : Pat < 2244 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 2245 imm:$offset, 0, 0, imm:$glc, imm:$slc, 2246 imm:$tfe)), 2247 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), 2248 (as_i1imm $slc), (as_i1imm $tfe)) 2249 >; 2250 2251 def : Pat < 2252 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 2253 imm, 1, 0, imm:$glc, imm:$slc, 2254 imm:$tfe)), 2255 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc), 2256 (as_i1imm $tfe)) 2257 >; 2258 2259 def : Pat < 2260 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 2261 imm:$offset, 0, 1, imm:$glc, imm:$slc, 2262 imm:$tfe)), 2263 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), 2264 (as_i1imm $slc), (as_i1imm $tfe)) 2265 >; 2266 2267 def : Pat < 2268 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset, 2269 imm, 1, 1, imm:$glc, imm:$slc, 2270 imm:$tfe)), 2271 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc), 2272 (as_i1imm $tfe)) 2273 >; 2274} 2275 2276defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN, 2277 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>; 2278defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN, 2279 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>; 2280defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN, 2281 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>; 2282 2283//===----------------------------------------------------------------------===// 2284// MTBUF Patterns 2285//===----------------------------------------------------------------------===// 2286 2287// TBUFFER_STORE_FORMAT_*, addr64=0 2288class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 2289 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 2290 i32:$soffset, imm:$inst_offset, imm:$dfmt, 2291 imm:$nfmt, imm:$offen, imm:$idxen, 2292 imm:$glc, imm:$slc, imm:$tfe), 2293 (opcode 2294 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 2295 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 2296 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 2297>; 2298 2299def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 2300def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 2301def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 2302def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 2303 2304let Predicates = [isCI] in { 2305 2306// Sea island new arithmetic instructinos 2307let neverHasSideEffects = 1 in { 2308defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64", 2309 [(set f64:$dst, (ftrunc f64:$src0))] 2310>; 2311defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64", 2312 [(set f64:$dst, (fceil f64:$src0))] 2313>; 2314defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64", 2315 [(set f64:$dst, (ffloor f64:$src0))] 2316>; 2317defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64", 2318 [(set f64:$dst, (frint f64:$src0))] 2319>; 2320 2321defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>; 2322defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>; 2323defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>; 2324def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>; 2325 2326// XXX - Does this set VCC? 2327def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>; 2328} // End neverHasSideEffects = 1 2329 2330// Remaining instructions: 2331// FLAT_* 2332// S_CBRANCH_CDBGUSER 2333// S_CBRANCH_CDBGSYS 2334// S_CBRANCH_CDBGSYS_OR_USER 2335// S_CBRANCH_CDBGSYS_AND_USER 2336// S_DCACHE_INV_VOL 2337// V_EXP_LEGACY_F32 2338// V_LOG_LEGACY_F32 2339// DS_NOP 2340// DS_GWS_SEMA_RELEASE_ALL 2341// DS_WRAP_RTN_B32 2342// DS_CNDXCHG32_RTN_B64 2343// DS_WRITE_B96 2344// DS_WRITE_B128 2345// DS_CONDXCHG32_RTN_B128 2346// DS_READ_B96 2347// DS_READ_B128 2348// BUFFER_LOAD_DWORDX3 2349// BUFFER_STORE_DWORDX3 2350 2351} // End Predicates = [isCI] 2352 2353 2354/********** ====================== **********/ 2355/********** Indirect adressing **********/ 2356/********** ====================== **********/ 2357 2358multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> { 2359 2360 // 1. Extract with offset 2361 def : Pat< 2362 (vector_extract vt:$vec, (add i32:$idx, imm:$off)), 2363 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) 2364 >; 2365 2366 // 2. Extract without offset 2367 def : Pat< 2368 (vector_extract vt:$vec, i32:$idx), 2369 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) 2370 >; 2371 2372 // 3. Insert with offset 2373 def : Pat< 2374 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)), 2375 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) 2376 >; 2377 2378 // 4. Insert without offset 2379 def : Pat< 2380 (vector_insert vt:$vec, eltvt:$val, i32:$idx), 2381 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) 2382 >; 2383} 2384 2385defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>; 2386defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>; 2387defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>; 2388defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>; 2389 2390defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>; 2391defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>; 2392defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>; 2393defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>; 2394 2395/********** =============== **********/ 2396/********** Conditions **********/ 2397/********** =============== **********/ 2398 2399def : Pat< 2400 (i1 (setcc f32:$src0, f32:$src1, SETO)), 2401 (V_CMP_O_F32_e64 $src0, $src1) 2402>; 2403 2404def : Pat< 2405 (i1 (setcc f32:$src0, f32:$src1, SETUO)), 2406 (V_CMP_U_F32_e64 $src0, $src1) 2407>; 2408 2409//===----------------------------------------------------------------------===// 2410// Conversion Patterns 2411//===----------------------------------------------------------------------===// 2412 2413def : Pat<(i32 (sext_inreg i32:$src, i1)), 2414 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16 2415 2416// TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it 2417// might not be worth the effort, and will need to expand to shifts when 2418// fixing SGPR copies. 2419 2420// Handle sext_inreg in i64 2421def : Pat < 2422 (i64 (sext_inreg i64:$src, i1)), 2423 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2424 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16 2425 (S_MOV_B32 -1), sub1) 2426>; 2427 2428def : Pat < 2429 (i64 (sext_inreg i64:$src, i8)), 2430 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2431 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0), 2432 (S_MOV_B32 -1), sub1) 2433>; 2434 2435def : Pat < 2436 (i64 (sext_inreg i64:$src, i16)), 2437 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2438 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0), 2439 (S_MOV_B32 -1), sub1) 2440>; 2441 2442//===----------------------------------------------------------------------===// 2443// Miscellaneous Patterns 2444//===----------------------------------------------------------------------===// 2445 2446def : Pat < 2447 (i32 (trunc i64:$a)), 2448 (EXTRACT_SUBREG $a, sub0) 2449>; 2450 2451def : Pat < 2452 (i1 (trunc i32:$a)), 2453 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1) 2454>; 2455 2456// V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector 2457// case, the sgpr-copies pass will fix this to use the vector version. 2458def : Pat < 2459 (i32 (addc i32:$src0, i32:$src1)), 2460 (S_ADD_I32 $src0, $src1) 2461>; 2462 2463//============================================================================// 2464// Miscellaneous Optimization Patterns 2465//============================================================================// 2466 2467def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>; 2468 2469} // End isSI predicate 2470