SIRegisterInfo.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief SI implementation of the TargetRegisterInfo class.
12//
13//===----------------------------------------------------------------------===//
14
15
16#include "SIRegisterInfo.h"
17#include "AMDGPUTargetMachine.h"
18#include "SIInstrInfo.h"
19
20using namespace llvm;
21
22SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm)
23: AMDGPURegisterInfo(tm),
24  TM(tm)
25  { }
26
27BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
28  BitVector Reserved(getNumRegs());
29  Reserved.set(AMDGPU::EXEC);
30  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
31  const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo());
32  TII->reserveIndirectRegisters(Reserved, MF);
33  return Reserved;
34}
35
36unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
37                                             MachineFunction &MF) const {
38  return RC->getNumRegs();
39}
40
41const TargetRegisterClass *
42SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
43  switch (rc->getID()) {
44  case AMDGPU::GPRF32RegClassID:
45    return &AMDGPU::VReg_32RegClass;
46  default: return rc;
47  }
48}
49
50const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
51                                                                   MVT VT) const {
52  switch(VT.SimpleTy) {
53    default:
54    case MVT::i32: return &AMDGPU::VReg_32RegClass;
55  }
56}
57
58unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
59  return getEncodingValue(Reg) & 0xff;
60}
61
62const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
63  assert(!TargetRegisterInfo::isVirtualRegister(Reg));
64
65  const TargetRegisterClass *BaseClasses[] = {
66    &AMDGPU::VReg_32RegClass,
67    &AMDGPU::SReg_32RegClass,
68    &AMDGPU::VReg_64RegClass,
69    &AMDGPU::SReg_64RegClass,
70    &AMDGPU::SReg_128RegClass,
71    &AMDGPU::SReg_256RegClass
72  };
73
74  for (unsigned i = 0, e = sizeof(BaseClasses) /
75                           sizeof(const TargetRegisterClass*); i != e; ++i) {
76    if (BaseClasses[i]->contains(Reg)) {
77      return BaseClasses[i];
78    }
79  }
80  return NULL;
81}
82
83bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
84  if (!RC) {
85    return false;
86  }
87  return !hasVGPRs(RC);
88}
89
90bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
91  return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
92         getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
93         getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
94         getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
95         getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
96         getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
97}
98
99const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
100                                         const TargetRegisterClass *SRC) const {
101    if (hasVGPRs(SRC)) {
102      return SRC;
103    } else if (SRC == &AMDGPU::SCCRegRegClass) {
104      return &AMDGPU::VCCRegRegClass;
105    } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
106      return &AMDGPU::VReg_32RegClass;
107    } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
108      return &AMDGPU::VReg_64RegClass;
109    } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
110      return &AMDGPU::VReg_128RegClass;
111    } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
112      return &AMDGPU::VReg_256RegClass;
113    } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
114      return &AMDGPU::VReg_512RegClass;
115    }
116    return NULL;
117}
118
119const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
120                         const TargetRegisterClass *RC, unsigned SubIdx) const {
121  if (SubIdx == AMDGPU::NoSubRegister)
122    return RC;
123
124  // If this register has a sub-register, we can safely assume it is a 32-bit
125  // register, because all of SI's sub-registers are 32-bit.
126  if (isSGPRClass(RC)) {
127    return &AMDGPU::SGPR_32RegClass;
128  } else {
129    return &AMDGPU::VGPR_32RegClass;
130  }
131}
132