SIRegisterInfo.cpp revision b52bf6a3b31596a309f4b12884522e9b4a344654 
1//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief SI implementation of the TargetRegisterInfo class.
12//
13//===----------------------------------------------------------------------===//
14
15
16#include "SIRegisterInfo.h"
17#include "AMDGPUTargetMachine.h"
18
19using namespace llvm;
20
21SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm)
22: AMDGPURegisterInfo(tm),
23  TM(tm)
24  { }
25
26BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
27  BitVector Reserved(getNumRegs());
28  Reserved.set(AMDGPU::EXEC);
29  return Reserved;
30}
31
32unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
33                                             MachineFunction &MF) const {
34  return RC->getNumRegs();
35}
36
37const TargetRegisterClass *
38SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
39  switch (rc->getID()) {
40  case AMDGPU::GPRF32RegClassID:
41    return &AMDGPU::VReg_32RegClass;
42  default: return rc;
43  }
44}
45
46const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
47                                                                   MVT VT) const {
48  switch(VT.SimpleTy) {
49    default:
50    case MVT::i32: return &AMDGPU::VReg_32RegClass;
51  }
52}
53
54const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
55  assert(!TargetRegisterInfo::isVirtualRegister(Reg));
56
57  const TargetRegisterClass *BaseClasses[] = {
58    &AMDGPU::VReg_32RegClass,
59    &AMDGPU::SReg_32RegClass,
60    &AMDGPU::VReg_64RegClass,
61    &AMDGPU::SReg_64RegClass,
62    &AMDGPU::SReg_128RegClass,
63    &AMDGPU::SReg_256RegClass
64  };
65
66  for (unsigned i = 0, e = sizeof(BaseClasses) /
67                           sizeof(const TargetRegisterClass*); i != e; ++i) {
68    if (BaseClasses[i]->contains(Reg)) {
69      return BaseClasses[i];
70    }
71  }
72  return NULL;
73}
74
75bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
76  if (!RC) {
77    return false;
78  }
79  return !hasVGPRs(RC);
80}
81
82bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
83  return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
84         getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
85         getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
86         getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
87         getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
88}
89
90const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
91                                         const TargetRegisterClass *SRC) const {
92    if (hasVGPRs(SRC)) {
93      return SRC;
94    } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
95      return &AMDGPU::VReg_32RegClass;
96    } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
97      return &AMDGPU::VReg_64RegClass;
98    } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
99      return &AMDGPU::VReg_128RegClass;
100    } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
101      return &AMDGPU::VReg_256RegClass;
102    } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
103      return &AMDGPU::VReg_512RegClass;
104    }
105    return NULL;
106}
107
108const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
109                         const TargetRegisterClass *RC, unsigned SubIdx) const {
110  if (SubIdx == AMDGPU::NoSubRegister)
111    return RC;
112
113  // If this register has a sub-register, we can safely assume it is a 32-bit
114  // register, becuase all of SI's sub-registers are 32-bit.
115  if (isSGPRClass(RC)) {
116    return &AMDGPU::SGPR_32RegClass;
117  } else {
118    return &AMDGPU::VGPR_32RegClass;
119  }
120}
121