SIRegisterInfo.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief SI implementation of the TargetRegisterInfo class.
12//
13//===----------------------------------------------------------------------===//
14
15
16#include "SIRegisterInfo.h"
17#include "AMDGPUTargetMachine.h"
18#include "SIInstrInfo.h"
19
20using namespace llvm;
21
22SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm)
23: AMDGPURegisterInfo(tm),
24  TM(tm)
25  { }
26
27BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
28  BitVector Reserved(getNumRegs());
29  Reserved.set(AMDGPU::EXEC);
30  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
31  const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo());
32  TII->reserveIndirectRegisters(Reserved, MF);
33  return Reserved;
34}
35
36unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
37                                             MachineFunction &MF) const {
38  return RC->getNumRegs();
39}
40
41const TargetRegisterClass *
42SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
43  switch (rc->getID()) {
44  case AMDGPU::GPRF32RegClassID:
45    return &AMDGPU::VReg_32RegClass;
46  default: return rc;
47  }
48}
49
50const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
51                                                                   MVT VT) const {
52  switch(VT.SimpleTy) {
53    default:
54    case MVT::i32: return &AMDGPU::VReg_32RegClass;
55  }
56}
57
58unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
59  return getEncodingValue(Reg) & 0xff;
60}
61
62const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
63  assert(!TargetRegisterInfo::isVirtualRegister(Reg));
64
65  const TargetRegisterClass *BaseClasses[] = {
66    &AMDGPU::VReg_32RegClass,
67    &AMDGPU::SReg_32RegClass,
68    &AMDGPU::VReg_64RegClass,
69    &AMDGPU::SReg_64RegClass,
70    &AMDGPU::SReg_128RegClass,
71    &AMDGPU::SReg_256RegClass
72  };
73
74  for (const TargetRegisterClass *BaseClass : BaseClasses) {
75    if (BaseClass->contains(Reg)) {
76      return BaseClass;
77    }
78  }
79  return nullptr;
80}
81
82bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
83  if (!RC) {
84    return false;
85  }
86  return !hasVGPRs(RC);
87}
88
89bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
90  return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
91         getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
92         getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
93         getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
94         getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
95         getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
96}
97
98const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
99                                         const TargetRegisterClass *SRC) const {
100    if (hasVGPRs(SRC)) {
101      return SRC;
102    } else if (SRC == &AMDGPU::SCCRegRegClass) {
103      return &AMDGPU::VCCRegRegClass;
104    } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
105      return &AMDGPU::VReg_32RegClass;
106    } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
107      return &AMDGPU::VReg_64RegClass;
108    } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
109      return &AMDGPU::VReg_128RegClass;
110    } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
111      return &AMDGPU::VReg_256RegClass;
112    } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
113      return &AMDGPU::VReg_512RegClass;
114    }
115    return nullptr;
116}
117
118const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
119                         const TargetRegisterClass *RC, unsigned SubIdx) const {
120  if (SubIdx == AMDGPU::NoSubRegister)
121    return RC;
122
123  // If this register has a sub-register, we can safely assume it is a 32-bit
124  // register, because all of SI's sub-registers are 32-bit.
125  if (isSGPRClass(RC)) {
126    return &AMDGPU::SGPR_32RegClass;
127  } else {
128    return &AMDGPU::VGPR_32RegClass;
129  }
130}
131
132unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
133                                          const TargetRegisterClass *SubRC,
134                                          unsigned Channel) const {
135  unsigned Index = getHWRegIndex(Reg);
136  return SubRC->getRegister(Index + Channel);
137}
138