SIRegisterInfo.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for SIRegisterInfo
12//
13//===----------------------------------------------------------------------===//
14
15
16#ifndef SIREGISTERINFO_H_
17#define SIREGISTERINFO_H_
18
19#include "AMDGPURegisterInfo.h"
20
21namespace llvm {
22
23class AMDGPUTargetMachine;
24
25struct SIRegisterInfo : public AMDGPURegisterInfo {
26  AMDGPUTargetMachine &TM;
27
28  SIRegisterInfo(AMDGPUTargetMachine &tm);
29
30  BitVector getReservedRegs(const MachineFunction &MF) const override;
31
32  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
33                               MachineFunction &MF) const override;
34
35  /// \param RC is an AMDIL reg class.
36  ///
37  /// \returns the SI register class that is equivalent to \p RC.
38  const TargetRegisterClass *
39    getISARegClass(const TargetRegisterClass *RC) const override;
40
41  /// \brief get the register class of the specified type to use in the
42  /// CFGStructurizer
43  const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
44
45  unsigned getHWRegIndex(unsigned Reg) const override;
46
47  /// \brief Return the 'base' register class for this register.
48  /// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
49  const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
50
51  /// \returns true if this class contains only SGPR registers
52  bool isSGPRClass(const TargetRegisterClass *RC) const;
53
54  /// \returns true if this class contains VGPR registers.
55  bool hasVGPRs(const TargetRegisterClass *RC) const;
56
57  /// \returns A VGPR reg class with the same width as \p SRC
58  const TargetRegisterClass *getEquivalentVGPRClass(
59                                          const TargetRegisterClass *SRC) const;
60
61  /// \returns The register class that is used for a sub-register of \p RC for
62  /// the given \p SubIdx.  If \p SubIdx equals NoSubRegister, \p RC will
63  /// be returned.
64  const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
65                                            unsigned SubIdx) const;
66
67  /// \p Channel This is the register channel (e.g. a value from 0-16), not the
68  ///            SubReg index.
69  /// \returns The sub-register of Reg that is in Channel.
70  unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
71                            unsigned Channel) const;
72};
73
74} // End namespace llvm
75
76#endif // SIREGISTERINFO_H_
77