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..12-Mar-20154 KiB

AsmParser/12-Mar-20154 KiB

CMakeLists.txt12-Mar-20151.2 KiB

DelaySlotFiller.cpp12-Mar-201514.1 KiB

Disassembler/12-Mar-20154 KiB

InstPrinter/12-Mar-20154 KiB

LLVMBuild.txt12-Mar-20151 KiB

Makefile12-Mar-2015822

MCTargetDesc/12-Mar-20154 KiB

README.txt12-Mar-20151.5 KiB

Sparc.h12-Mar-20154.4 KiB

Sparc.td12-Mar-20153.9 KiB

SparcAsmPrinter.cpp12-Mar-201516.9 KiB

SparcCallingConv.td12-Mar-20155.4 KiB

SparcCodeEmitter.cpp12-Mar-20159.6 KiB

SparcFrameLowering.cpp12-Mar-20158.7 KiB

SparcFrameLowering.h12-Mar-20151.9 KiB

SparcInstr64Bit.td12-Mar-201523.2 KiB

SparcInstrAliases.td12-Mar-201513 KiB

SparcInstrFormats.td12-Mar-20158.8 KiB

SparcInstrInfo.cpp12-Mar-201515.2 KiB

SparcInstrInfo.h12-Mar-20153.8 KiB

SparcInstrInfo.td12-Mar-201549 KiB

SparcInstrVIS.td12-Mar-201511.1 KiB

SparcISelDAGToDAG.cpp12-Mar-20157.6 KiB

SparcISelLowering.cpp12-Mar-2015126 KiB

SparcISelLowering.h12-Mar-20158 KiB

SparcJITInfo.cpp12-Mar-201511.4 KiB

SparcJITInfo.h12-Mar-20152.1 KiB

SparcMachineFunctionInfo.cpp12-Mar-2015448

SparcMachineFunctionInfo.h12-Mar-20151.8 KiB

SparcMCInstLower.cpp12-Mar-20153.3 KiB

SparcRegisterInfo.cpp12-Mar-20157.1 KiB

SparcRegisterInfo.h12-Mar-20151.8 KiB

SparcRegisterInfo.td12-Mar-20158.1 KiB

SparcRelocations.h12-Mar-20151.4 KiB

SparcSelectionDAGInfo.cpp12-Mar-2015746

SparcSelectionDAGInfo.h12-Mar-2015824

SparcSubtarget.cpp12-Mar-20153.3 KiB

SparcSubtarget.h12-Mar-20153.1 KiB

SparcTargetMachine.cpp12-Mar-20153.7 KiB

SparcTargetMachine.h12-Mar-20152.8 KiB

SparcTargetObjectFile.cpp12-Mar-20151.6 KiB

SparcTargetObjectFile.h12-Mar-2015996

SparcTargetStreamer.h12-Mar-20151.4 KiB

TargetInfo/12-Mar-20154 KiB

README.txt

1
2To-do
3-----
4
5* Keep the address of the constant pool in a register instead of forming its
6  address all of the time.
7* We can fold small constant offsets into the %hi/%lo references to constant
8  pool addresses as well.
9* When in V9 mode, register allocate %icc[0-3].
10* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
11* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
12  not clear how to write a pattern for this though:
13
14float %t1(int %a, int* %p) {
15        %C = seteq int %a, 0
16        br bool %C, label %T, label %F
17T:
18        store int 123, int* %p
19        br label %F
20F:
21        ret float undef
22}
23
24codegens to this:
25
26t1:
27        save -96, %o6, %o6
281)      subcc %i0, 0, %l0
291)      bne .LBBt1_2    ! F
30        nop
31.LBBt1_1:       ! T
32        or %g0, 123, %l0
33        st %l0, [%i1]
34.LBBt1_2:       ! F
35        restore %g0, %g0, %g0
36        retl
37        nop
38
391) should be replaced with a brz in V9 mode.
40
41* Same as above, but emit conditional move on register zero (p192) in V9
42  mode.  Testcase:
43
44int %t1(int %a, int %b) {
45        %C = seteq int %a, 0
46        %D = select bool %C, int %a, int %b
47        ret int %D
48}
49
50* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
51  with the Y register, if they are faster.
52
53* Codegen bswap(load)/store(bswap) -> load/store ASI
54
55* Implement frame pointer elimination, e.g. eliminate save/restore for
56  leaf fns.
57* Fill delay slots
58
59* Implement JIT support
60
61* Use %g0 directly to materialize 0. No instruction is required.
62